UltraScale Architecture Memory Resources

Chapter 2: Built-in FIFO
FIFO might be reported as fewer than there actually are in the FIFO. However, because the
PROGEMPTY flag is synchronous to the RDCLK domain, it is generally used to determine
how many locations in the FIFO are available to be read, so the under-reporting of
PROGEMPTY guarantees that the FIFO never underflows.
The number of clock cycles required for a write operation to cause PROGEMPTY to deassert
depends on the FIFO configuration. For an independent-clocks FIFO, a write operation is
first synchronized internally to the RDCLK domain before it can influence the status of the
PROGEMPTY flag, resulting in a latency from the write operation to the deassertion of
PROGEMPTY that is a combination of a few write clocks followed by a few read clocks.
The PROGEMPTY flag is synchronous to the RDCLK domain and is intended as a status
signal for logic reading from the FIFO.
Read Error Flag
After the Empty flag has been asserted, any further read attempts do not increment the
read address pointer but do trigger the Read Error (RDERR) flag. A RDERR also occurs if a
write operation is performed while RDRSTBUSY is asserted. The RDERR flag is deasserted
when Read Enable or Empty is deasserted. The RDERR flag is synchronous to RDCLK.
Full Flag
If FULL is asserted, the FIFO has no room for any additional words to be written to the FIFO,
and any additional write operations cause a write error (WRERR=1). When reading from a
full FIFO, the number of clock cycles required for the FULL output to deassert depend on the
FIFO configuration. For an independent-clocks FIFO, a read operation must be synchronized
internally to the WRCLK domain before it can influence the status of the FULL flag, resulting
in a latency from the read operation to the deassertion of FULL that is a combination of a
few read clocks followed by a few write clocks.
The FULL flag is synchronous to the WRCLK domain and is intended as a handshaking signal
for logic writing to the FIFO.
Write Error Flag
After the Full flag is asserted, any further write attempts do not increment the write address
pointer but do trigger the Write Error (WRERR) flag. A WRERR also occurs if a write
operation is performed while WRRSTBUSY is asserted. The WRERR flag is deasserted when
Write Enable or Full is deasserted. This signal is synchronous to WRCLK.
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UG573 (v1.2) February 24, 2015