UltraScale Architecture Memory Resources

Chapter 2
Built-in FIFO
Overview
Many designs use block RAMs to implement FIFOs. Common-clock or independent-clock
FIFOs can be easily implemented with the dedicated logic in the block RAM. This eliminates
the need for additional CLB logic for counter, comparator, or status flag generation, and
uses just one block RAM resource per FIFO. Both standard and first-word fall-through
(FWFT) modes are supported.
The FIFO can be configured as an 18 Kb or 36 Kb memory. For the 18 Kb mode, the
supported configurations are 4K x 4, 2K x 9, 1K x 18, and 512 x 36. The supported
configurations for the 36 Kb FIFO are 8K x 4, 4K x 9, 2K x 18, 1K x 36, and 512 x 72. The FIFO
ports can now be configured in an asymmetrical fashion.
The block RAM can be configured as a first-in/first-out (FIFO) memory with common or
independent read and write clocks. Port A of the block RAM is used as a FIFO read port, and
Port B is a FIFO write port. Data is read from the FIFO on the rising edge of the read clock
and written to the FIFO on the rising edge of the write clock.
Independent-Clock/Dual-Clock FIFO
The independent-clock FIFO (also referred to as a dual-clock or sometimes asynchronous
FIFO) is a first-in/first-out queue where the write interface and the read interface exist in
different clock domains. To configure the FIFO as an independent-clock FIFO, the attribute
CLOCK_DOMAINS should be set to INDEPENDENT.
The independent-clock FIFO offers a simple write interface and a simple read interface, both
of which could be free-running clocks with no frequency or phase relationship between the
clocks. As such, it is ideal for situations where:
• WRCLK and RDCLK have different but related frequencies
• WRCLK and RDCLK are out-of-phase with each other
• WRCLK and RDCLK are completely asynchronous (have no relationship)
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UG573 (v1.2) February 24, 2015