UltraScale Architecture Memory Resources

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Chapter 1: Block RAM Resources Additional Block RAM Features Optional Output Registers The optional output registers improve design performance by eliminating routing delay to the configurable logic block (CLB) flip-flops for pipelined operation. An independent clock and clock enable input is provided for these output registers. As a result, the output data registers hold the value independent of the input register operation. Figure 1-5 shows the optional output register. X-Ref Target - Figure 1-5 DOUT Address DIN Register Memory Array (common to both ports) D Q Latches D Q Register WE EN Write Strobe Read Strobe Control Engine Latch Enable CLK Optional Inverter Configurable Options UG573_c1_05_060613 Figure 1-5: Block RAM Logic Diagram (One Port Shown) Independent Read and Write Port Width Selection Each block RAM port has control over data width and address depth (aspect ratio). The true dual-port block RAM extends this flexibility to read and write where each individual port can be configured with different data bit widths. For example, port A can have a 36-bit read width and a 9-bit write width, and port B can have an 18-bit read width and a 36-bit write width. If the read port width differs from the write port width and is configured in WRITE_FIRST mode, DOUT shows valid new data for all the enabled write bytes. The DOUT port outputs the original data stored in memory for all not-enabled bytes. Independent read and write port width selection increases the efficiency of implementing a content addressable memory (CAM) in block RAM. This option is available for all UltraScale architecture-based devices true dual-port RAM port sizes and modes. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 14 UG573 (v1.2) February 24, 2015
Chapter 1: Block RAM Resources Simple Dual-Port Block RAM Each 18 Kb block and 36 Kb block can also be configured in a SDP RAM mode. In this mode, the block RAM port width doubles to 36 bits for the 18 Kb block RAM and 72 bits for the 36 Kb block RAM. When the block RAM is used as SDP memory, independent read and write operations can occur simultaneously, where port A is designated as the read port and port B as the write port. When the read and write port access the same data location at the same time, it is treated as a collision, identical to the port collision in true dual-port mode. UltraScale architecture-based devices support these modes when the block RAM is used as SDP memory (READ_FIRST, WRITE_FIRST, NO_CHANGE). Figure 1-6 shows the simple dual-port data flow for RAMB36 when the block RAM is used as SDP memory. X-Ref Target - Figure 1-6 CASDOUT CASDOUTP 64 8 15 32 4 DIN DINP RDADDR DOUT DOUTP 64 8 RDADDREN RDCLK Sleep 8 15 RDEN REGCE RSTREG RSTRAM WE WRADDR 36 Kb Memory Array WRADDREN WRCLK WREN 32 4 CASDIN CASDINP UG573_c1_06_062314 Figure 1-6: RAMB36 Usage in a Simple Dual-Port Data Flow UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 15 UG573 (v1.2) February 24, 2015
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Chapter 2: Built-in FIFO FWFT Mode
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Appendix A Additional Resources and
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UltraScale Architecture Memory Resources

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