UltraScale Architecture Memory Resources

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Chapter 2: Built-in FIFO FIFO Architecture: Top-Level View Figure 2-1 shows a top-level view of the FIFO. The read pointer, write pointer, and status flag logic are dedicated for FIFO use only. X-Ref Target - Figure 2-1 WRCOUNT Write Pointer waddr Block RAM raddr Read Pointer RDCOUNT DIN/DINP mem_wr mem_rd DOUT/DOUTP WRCLK WREN RST Write Status Flag Logic sync Read Status Flag Logic RDCLK RDEN PROGFULL EMPTY FULL WRERR RDERR PROGEMPTY UG573_c2_01_111312 Figure 2-1: Top-Level View of FIFO in Block RAM FIFO Port Width and Depth The FIFOs support asymmetric read and write ports based on the block RAM’s asymmetric port capability to support different port widths for each port. The FIFO18E2 supports independent read/write port width combinations of 4, 8, 16, and 32, which can be expanded to 9, 18, and 36 when utilizing the DINP bits. The FIFO36E2 supports independent read/write port width combinations of 4, 8, 16, 32, and 64, which can be expanded to 9, 18, 36, and 72 when utilizing the DINP bits. When considering features such as output register stages, FWFT mode, or asymmetric ports, FIFO depth varies. When using asymmetric port widths, the FIFO depth differs depending on the number of write words in the WRCLK domain and the number of read words in the RDCLK domain. FIFO depth in the WRCLK domain is the number of write words that, when written to a FIFO, causes it to go FULL. In a special case, if the read port is narrower than the write port, it is possible that a partial word exists in the FIFO, causing FULL to assert one clock earlier than expected. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 52 UG573 (v1.2) February 24, 2015
Chapter 2: Built-in FIFO Table 2-2: Write Port Width FIFO depth in the RDCLK domain is the number of read words that would be in the FIFO if the FIFO were FULL. Because the read port width might not be the same as the write port width, the depth differs when expressed in the RDCLK domain. Also, in a special case where the write port is narrower than the read port, it is possible that a partial word exists in the FIFO that is not available to be read and therefore does not count toward the FIFO depth in the RDCLK domain. The FIFO depth can be used to understand and calculate: • When using WRCOUNT, the depth determines how many more writes can be performed before the FIFO goes FULL (in the WRCLK domain). This calculation is: ° “FIFO Depth” minus “Number of Words in FIFO” where the number of words available in the FIFO is given by the WRCOUNT (for WRCOUNT_TYPE SIMPLE_DATACOUNT mode for standard FIFOs with no output stages, or EXTENDED_DATACOUNT count mode when using output stages or FWFT). • How to calculate the PROG_FULL_THRESH to set the threshold at a specific distance from FULL. • Determine the range of PROG_FULL_THRESH. • Determine the range of PROG_EMPTY_THRESH. • Determine all cases of FULL. Table 2-2 to Table 2-5 list the FIFO depths in both the WRCLK and RDCLK domains for all possible FIFO configurations and widths. Note: The tables do not cover the EN_ECC_PIPE = TRUE configurations, which increase read port depth by 1. Independent Clocks FIFO Port Width and Depths – FIFO36E2 Read Port Width Latch Mode (REGISTER_MODE = "UNREGISTERED") Write Port Depth Register Mode (REGISTER_MODE = "REGISTERED") Standard FWFT Standard FWFT Read Port Depth Write Port Depth Read Port Depth Write Port Depth Read Port Depth Write Port Depth Read Port Depth 4 4 8191 8191 8192 8192 8192 8192 8193 8193 4 8 8191 4095 (1) 8193 4096 (1) 8193 4096 (1) 8195 4097 (1) 4 16 8191 2047 (1) 8195 2048 (1) 8195 2048 (1) 8199 2049 (1) 4 32 8191 1023 (1) 8199 1024 (1) 8199 1024 (1) 8207 1025 (1) 4 64 8191 511 (1) 8207 512 (1) 8207 512 (1) 8223 513 (1) 8 4 4095 8190 4095 (2) 8191 4095 (2) 8191 4096 8192 9 9 4095 4095 4096 4096 4096 4096 4097 4097 9 18 4095 2047 (1) 4097 2048 (1) 4097 2048 (1) 4099 2049 (1) UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 53 UG573 (v1.2) February 24, 2015
Page 1 and 2: UltraScale Architecture Memory Reso
Page 3 and 4: Table of Contents Revision History
Page 5 and 6: Chapter 1 Block RAM Resources Intro
Page 7 and 8: Chapter 1: Block RAM Resources •
Page 9 and 10: Chapter 1: Block RAM Resources •
Page 11 and 12: Chapter 1: Block RAM Resources Tabl
Page 13 and 14: Chapter 1: Block RAM Resources NO_C
Page 15 and 16: Chapter 1: Block RAM Resources Simp
Page 17 and 18: Chapter 1: Block RAM Resources capa
Page 19 and 20: Chapter 1: Block RAM Resources Stan
Page 21 and 22: Chapter 1: Block RAM Resources Data
Page 23 and 24: Chapter 1: Block RAM Resources Byte
Page 25 and 26: Chapter 1: Block RAM Resources Figu
Page 29 and 30: Chapter 1: Block RAM Resources Regi
Page 33 and 34: Chapter 1: Block RAM Resources CASD
Page 39 and 40: Chapter 1: Block RAM Resources Cont
Page 41 and 42: Chapter 1: Block RAM Resources Read
Page 43 and 44: Chapter 1: Block RAM Resources Opti
Page 45 and 46: Chapter 1: Block RAM Resources Addi
Page 47 and 48: Chapter 1: Block RAM Resources Bloc
Page 49 and 50: Chapter 2 Built-in FIFO Overview Ma
Page 51: Chapter 2: Built-in FIFO Table 2-1:
Page 55 and 56: Chapter 2: Built-in FIFO Table 2-3:
Page 59 and 60: Chapter 2: Built-in FIFO Figure 2-3
Page 65 and 66: Chapter 2: Built-in FIFO FIFO18/36
Page 69 and 70: Chapter 2: Built-in FIFO • MIDDLE
Page 71 and 72: Chapter 2: Built-in FIFO FWFT Mode
Page 73 and 74: Chapter 2: Built-in FIFO FIFO might
Page 75 and 76: Chapter 2: Built-in FIFO the status
Page 77 and 78: Chapter 2: Built-in FIFO X-Ref Targ
Page 83 and 84: Chapter 3: Built-in Error Correctio
Page 89 and 90: Appendix A Additional Resources and

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