UltraScale Architecture Memory Resources

Chapter 3: Built-in Error Correction
• In ECC configuration, the block RAM can be in either READ_FIRST, WRITE_FIRST, and
NO_CHANGE mode. See also Address Collision in Chapter 1.
UltraScale architecture-based devices have an ECC pipeline mode. This is in addition to
the optional registers on the outputs. These registers effectively pipeline the decoder for
further improvement in maximum performance (F MAX ) and clock-to-out in latch mode. If
turned on, the latency increases by one clock cycle because while the current address is
read from the block RAM, the previous address is being decoded. The ECC pipeline register
has a user accessible ENABLE control but does not have a reset control. Asserting the
block RAM reset pins RSTRAM and RSTREG has no impact on this register, and the
previously registered data remains in the register. When using EN_ECC_PIPE = TRUE with
the FIFO, the FIFO controller always automatically manages the ECC pipeline register and
the associated ECCPIPECE pin. The effective read depth of the FIFO is increase by one word,
and the read clock to write flags EMPTY/PROGEMPTY deassertion latency also increase by
one. However, the read to DOUT latency does not change.
Top-Level View of the Block RAM ECC Architecture
Figure 3-1 shows the top-level view of a block RAM in ECC mode.
UltraScale Architecture Memory Resources www.xilinx.com
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UG573 (v1.2) February 24, 2015