UltraScale Architecture Memory Resources

Chapter 1: Block RAM Resources
Register Enable – REGCEAREGCE and REGCEB
The register enable pin (REGCE) controls the optional output register. When the block RAM
is in register mode, REGCE = 1 registers the output into a register at a clock edge. The
polarity of REGCE is not configurable (active-High). When used as SDP memory, the
REGCEA port is the REGCE.
Set/Reset
RSTREGARSTREG, RSTREGB, RSTRAMARSTRAM, and RSTRAMB
In latch mode, the RSTRAM pin synchronously forces the data output latches to contain the
value SRVAL. When the optional output registers are enabled (DO_REG = 1), the RSTREG
signal synchronously forces the data output registers containing the SRVAL value. The
priority of RSTREG over REGCE is determined using the RSTREG_PRIORITY attribute. The
data output latches or output registers are synchronously asserted to 0 or 1, including the
parity bit. Each port has an independent SRVAL[A|B] attribute of 36 bits. This operation does
not affect RAM memory cells and does not disturb write operations on the other port. The
polarity for both signals is configurable (active-High by default). When used as SDP
memory, the RSTREGA port is the RSTREG, and the RSTRAMA port is the RSTRAM.
Address Bus – ADDRARDADDR and ADDRBWRADDR
The address bus selects the memory cells for read or write. When used as SDP memory, the
ADDRA port is the RDADDR and the ADDRB port is the WRADDR. The data bit width of the
port determines the required address bus width for a single RAMB18E2 or RAMB36E2, as
shown in Table 1-7, Table 1-8, Table 1-9, and Table 1-10.
Table 1-7:
Port Data
Width
Port Aspect Ratio for RAMB18E2 (When Used as TDP Memory)
Port Address
Width
Depth
ADDR Bus
DIN Bus
DOUT Bus
DINP Bus
DOUTP Bus
1 14 16,384 [13:0] [0] NA
2 13 8,192 [13:1] [1:0] NA
4 12 4,096 [13:2] [3:0] NA
9 11 2,048 [13:3] [7:0] [0]
18 10 1,024 [13:4] [15:0] [1:0]
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UG573 (v1.2) February 24, 2015