UltraScale Architecture Memory Resources
ug573-ultrascale-memory-resources
ug573-ultrascale-memory-resources
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Chapter 2: Built-in FIFO<br />
Figure 2-11 shows a serial cascading example of three FIFOs.<br />
X-Ref Target - Figure 2-11<br />
CASCADE_ORDER = LAST<br />
REGISTERED<br />
CASDIN<br />
BRAM2 0<br />
1<br />
Optional<br />
Register<br />
0<br />
0<br />
1 DOUT<br />
1<br />
FIFO<br />
Read<br />
Interface<br />
CASCADE_ORDER = MIDDLE<br />
REGISTERED<br />
CASDIN<br />
BRAM1 0<br />
1<br />
Optional<br />
Register<br />
0<br />
0<br />
1 CASDOUT<br />
1<br />
CASCADE_ORDER = FIRST<br />
REGISTERED<br />
DIN0<br />
FIFO<br />
Write<br />
Interface<br />
BRAM0 0<br />
1<br />
Optional<br />
Register<br />
0<br />
0<br />
1 CASDOUT<br />
1<br />
UG573_c2_05_031513<br />
Figure 2-11:<br />
FIFO Serial Cascade<br />
IMPORTANT: In serial cascade mode, the multiplexer control signals are not accessible and are<br />
automatically configured.<br />
Aside from the dedicated data cascading pins CASDIN, CASDINP, CASDOUT, and<br />
CASDOUTP, the FIFO has four additional control pins to support serial cascading. These pins<br />
must be connected as follows:<br />
• CASNXTEMPTY output: The CASNXTEMPTY output of a cascaded FIFO with<br />
CASCADE_ORDER = FIRST or MIDDLE is the cascaded EMPTY output from the current<br />
FIFO to the next in the chain. CASNXTEMPTY connects to the CASPRVEMPTY input on<br />
the next FIFO in the chain (configured with CASCADE_ORDER = MIDDLE or LAST),<br />
allowing the next FIFO to be aware of when this FIFO is not EMPTY and available for<br />
reading.<br />
<strong>UltraScale</strong> <strong>Architecture</strong> <strong>Memory</strong> <strong>Resources</strong> www.xilinx.com<br />
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UG573 (v1.2) February 24, 2015