UltraScale Architecture Memory Resources

Chapter 2: Built-in FIFO
PROGFULL Flag
If PROGFULL is asserted, the number of words in the FIFO is greater than or equal to
PROG_FULL_THRESH.
Because of the inherent latencies in the FIFO, especially for the independent-clocks FIFO,
PROGFULL is always considered a pessimistic flag. This means that not all read operations
might have synchronized to the WRCLK domain, and therefore the words in the FIFO might
be reported as more than there actually are in the FIFO. However, because the PROGFULL
flag is synchronous to the WRCLK domain, PROGFULL is generally used to determine how
many locations in the FIFO are available to be written, so the over-reporting of PROGFULL
guarantees that too many words are never written to the FIFO.
The number of clock cycles required for a read operation to cause PROGFULL to deassert
depends on the FIFO configuration. For an independent-clocks FIFO, a read operation is
first synchronized internally to the WRCLK domain before it can influence the status of the
PROGFULL flag, resulting in a latency from the read operation to the deassertion of
PROGFULL that is a combination of a few read clocks followed by a few write clocks.
The PROGFULL flag is synchronous to the WRCLK domain and is intended as a status signal
for logic writing to the FIFO.
Flag Assertion/Deassertion and Flag Latencies
Flag assertion and deassertion timing depends on the configuration of the FIFO. The
common-clock FIFO configuration is not affected by the uncertainty of two unrelated clock
domains, and requires no synchronization between clock domains. Therefore, the internal
latencies from a write operation to the deassertion of EMPTY or PROGEMPTY, or from a read
operation to the deassertion of FULL or PROGFULL, are much faster than in an equivalent
independent-clock FIFO. Similarly, a FIFO configured with asymmetric ports has additional
latencies depending on the port width ratios of the read and write port. The configuration
of the REGISTER_MODE, FIRST_WORD_FALL_THROUGH, and EN_ECC_PIPE attributes can
increase the latency from a write operation to the deassertion of EMPTY up to three
additional RDCLK cycles.
Independent-clock FIFOs are synchronized between clock domains. Due to this internal
synchronization between the WRCLK domain and the RDCLK domain, certain transitions
take several clock cycles. For example, it takes several clock cycles (both WRCLK and RDCLK
clock cycles) for the write operation to synchronize to the RDCLK domain. Only after the
write operation is synchronized to the RDCLK domain is that write operation reflected in the
status of the RDCLK outputs EMPTY and PROGEMPTY, and possibly cause these flags to
deassert.
Similarly, the internal synchronization between the RDCLK domain and the WRCLK domain
also takes several clock cycles. For example, it takes several clock cycles (both RDCLK and
WRCLK clock cycles) for the read operation to synchronize to the WRCLK domain. Only after
the read operation is synchronized to the WRCLK domain is that read operation reflected in
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UG573 (v1.2) February 24, 2015