UltraScale Architecture Memory Resources

More documents

Recommendations

Info

Chapter 1: Block RAM Resources Table 1-3 lists the simple dual-port functions and descriptions. Table 1-3: DOUT DOUTP DIN DINP RDADDR RDCLK RDEN REGCE RSTREG RSTRAM WRADDR WRCLK WREN Sleep Simple Dual-Port Functions and Descriptions Port Function CASDIN[A|B] CASDINP[A|B] CASDOUT[A|B] CASDOUTP[A|B] RDADDREN/WRADDREN Notes: Data output bus. Cascadable Block RAM Data output parity bus. Data input bus. Data input parity bus. Read data address bus. Read data clock. Read port enable. Output register clock enable. Description Synchronous set/reset of the output registers. Synchronous set/reset of the output data latches. Write data address bus. Write data clock. Write port enable. Dynamic shutdown power saving. If Sleep is High, the block is in power-saving mode Cascade data input bus. Cascade parity input bus. Cascade data output bus. Cascade parity output bus. Address latching enable. If Low, the old address is latched. 1. For a more complete cascade data flow and port descriptions, see Cascadable Block RAM, page 16 and Block RAM Library Primitives, page 24. UltraScale architecture-based devices provide the capability to cascade data out from one RAMB36 to the next RAMB36 serially to make a deeper block RAM in a bottom-up fashion. The data out cascading feature is supported for all RAMB36 port widths. The block RAM cascade supports all the features supported by the RAMB36E2 module. Note: The 64K x 1 cascade functionality provided in previous architectures has been removed. The same 64K x 1 cascade feature can be achieved using the new cascade block RAM implementation. The data flow is always from lower block RAM to upper block RAM. All of the signal routings and the control logic for the cascading feature are implemented in hardware. Multiple block RAMs can be cascaded, as required. In cascade mode, a single, common clock source must drive the same block RAM inputs (RDCLK or WRCLK). Furthermore, the data cascade UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 16 UG573 (v1.2) February 24, 2015
Chapter 1: Block RAM Resources capability allows that the lower RAMB18 of the lower RAMB36 can be independently cascaded to the lower RAMB18 of the upper RAMB36. Similarly, the upper RAMB18 of lower RAMB36 can be cascaded to the upper RAMB18 of the upper RAMB36 site. IMPORTANT: All block RAMs in a cascade chain must have matching configurations for certain features (e.g., common inputs such as the port width must be identical). Figure 1-7 shows a high-level, conceptual view of four cascaded block RAMs. X-Ref Target - Figure 1-7 CASDIMUX CASOREGIMUX Data to the Next Block RAM CASDOMUX DINx BRAM3 CLK D Q DOUTx Final Output DINx BRAM2 CLK D Q DOUTx DINx BRAM1 CLK D Q DOUTx DINx BRAM0 CLK D Q DOUTx Data From the Previous Block RAM UG573_c1_07_061713 Figure 1-7: High-level View of the Block RAM Cascade Architecture The block RAM provides flexibility to support many different implementations of the cascade feature. The three multiplexers (Figure 1-7) that select datapaths and pipeline registers can be dynamically controlled with the input pins. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 17 UG573 (v1.2) February 24, 2015
Page 1 and 2: UltraScale Architecture Memory Reso
Page 3 and 4: Table of Contents Revision History
Page 5 and 6: Chapter 1 Block RAM Resources Intro
Page 7 and 8: Chapter 1: Block RAM Resources •
Page 9 and 10: Chapter 1: Block RAM Resources •
Page 11 and 12: Chapter 1: Block RAM Resources Tabl
Page 13 and 14: Chapter 1: Block RAM Resources NO_C
Page 15: Chapter 1: Block RAM Resources Simp
Page 19 and 20: Chapter 1: Block RAM Resources Stan
Page 21 and 22: Chapter 1: Block RAM Resources Data
Page 23 and 24: Chapter 1: Block RAM Resources Byte
Page 25 and 26: Chapter 1: Block RAM Resources Figu
Page 29 and 30: Chapter 1: Block RAM Resources Regi
Page 33 and 34: Chapter 1: Block RAM Resources CASD
Page 39 and 40: Chapter 1: Block RAM Resources Cont
Page 41 and 42: Chapter 1: Block RAM Resources Read
Page 43 and 44: Chapter 1: Block RAM Resources Opti
Page 45 and 46: Chapter 1: Block RAM Resources Addi
Page 47 and 48: Chapter 1: Block RAM Resources Bloc
Page 49 and 50: Chapter 2 Built-in FIFO Overview Ma
Page 51 and 52: Chapter 2: Built-in FIFO Table 2-1:
Page 59 and 60: Chapter 2: Built-in FIFO Figure 2-3
Page 65 and 66: Chapter 2: Built-in FIFO FIFO18/36
Page 67 and 68:
Chapter 2: Built-in FIFO Table 2-9:
Page 69 and 70:
Chapter 2: Built-in FIFO • MIDDLE
Page 71 and 72:
Chapter 2: Built-in FIFO FWFT Mode
Page 73 and 74:
Chapter 2: Built-in FIFO FIFO might
Page 75 and 76:
Chapter 2: Built-in FIFO the status
Page 77 and 78:
Chapter 2: Built-in FIFO X-Ref Targ
Page 79 and 80:
Chapter 2: Built-in FIFO Figure 2-1
Page 81 and 82:
Chapter 2: Built-in FIFO Figure 2-1
Page 83 and 84:
Chapter 3: Built-in Error Correctio
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Appendix A Additional Resources and
show all

UltraScale Architecture Memory Resources

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?