UltraScale Architecture Memory Resources
ug573-ultrascale-memory-resources
ug573-ultrascale-memory-resources
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Chapter 1: Block RAM <strong>Resources</strong><br />
Table 1-12: RAMB18/36 Unused Inputs (Cont’d)<br />
RAMB18/36 Constant Comments<br />
CASOREGIMUXA 0<br />
CASOREGIMUXB 0<br />
CASDIMUXA 0<br />
CASDIMUXB 0<br />
CASDOMUXEN_A 1<br />
CASDOMUXEN_B 1<br />
CASOREGIMUXEN_A 1<br />
CASOREGIMUXEN_B 1<br />
INJECTSBITERR 0<br />
INJECTDBITERR 0<br />
Block RAM Address Mapping<br />
Each port accesses the same set of 18,432 or 36,864 memory cells using an addressing<br />
scheme dependent on whether it is a RAMB18E2 or RAMB36E2. The physical RAM locations<br />
addressed for a particular width are determined using these formulae (of interest only when<br />
the two ports use different aspect ratios):<br />
END = ((ADDR + 1) × Width) –1<br />
START = ADDR × Width<br />
Table 1-13 shows low-order address mapping for each port width.<br />
Table 1-13:<br />
Port Address Mapping<br />
Port<br />
Width<br />
Parity<br />
Locations<br />
Data Locations<br />
1 N.A. 3<br />
1<br />
3<br />
0<br />
2<br />
9<br />
2<br />
8<br />
2<br />
7<br />
2<br />
6<br />
2<br />
5<br />
2<br />
4<br />
2<br />
3<br />
2<br />
2<br />
2<br />
1<br />
2<br />
0<br />
1<br />
9<br />
1<br />
8<br />
1<br />
7<br />
1<br />
6<br />
1<br />
5<br />
1<br />
4<br />
1<br />
3<br />
1<br />
2<br />
1<br />
1<br />
1<br />
0<br />
9 8 7 6 5 4 3 2 1 0<br />
2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />
4 7 6 5 4 3 2 1 0<br />
8 + 1 3 2 1 0 3 2 1 0<br />
16 +<br />
2<br />
32 +<br />
4<br />
1 0 1 0<br />
0 0<br />
<strong>UltraScale</strong> <strong>Architecture</strong> <strong>Memory</strong> <strong>Resources</strong> www.xilinx.com<br />
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UG573 (v1.2) February 24, 2015
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