UltraScale Architecture Memory Resources
ug573-ultrascale-memory-resources
ug573-ultrascale-memory-resources
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Chapter 2: Built-in FIFO<br />
Table 2-2:<br />
Write<br />
Port<br />
Width<br />
FIFO depth in the RDCLK domain is the number of read words that would be in the FIFO if<br />
the FIFO were FULL. Because the read port width might not be the same as the write port<br />
width, the depth differs when expressed in the RDCLK domain. Also, in a special case where<br />
the write port is narrower than the read port, it is possible that a partial word exists in the<br />
FIFO that is not available to be read and therefore does not count toward the FIFO depth in<br />
the RDCLK domain.<br />
The FIFO depth can be used to understand and calculate:<br />
• When using WRCOUNT, the depth determines how many more writes can be performed<br />
before the FIFO goes FULL (in the WRCLK domain). This calculation is:<br />
° “FIFO Depth” minus “Number of Words in FIFO” where the number of words<br />
available in the FIFO is given by the WRCOUNT (for WRCOUNT_TYPE<br />
SIMPLE_DATACOUNT mode for standard FIFOs with no output stages, or<br />
EXTENDED_DATACOUNT count mode when using output stages or FWFT).<br />
• How to calculate the PROG_FULL_THRESH to set the threshold at a specific distance<br />
from FULL.<br />
• Determine the range of PROG_FULL_THRESH.<br />
• Determine the range of PROG_EMPTY_THRESH.<br />
• Determine all cases of FULL.<br />
Table 2-2 to Table 2-5 list the FIFO depths in both the WRCLK and RDCLK domains for all<br />
possible FIFO configurations and widths.<br />
Note: The tables do not cover the EN_ECC_PIPE = TRUE configurations, which increase read port<br />
depth by 1.<br />
Independent Clocks FIFO Port Width and Depths – FIFO36E2<br />
Read<br />
Port<br />
Width<br />
Latch Mode<br />
(REGISTER_MODE = "UNREGISTERED")<br />
Write<br />
Port<br />
Depth<br />
Register Mode<br />
(REGISTER_MODE = "REGISTERED")<br />
Standard FWFT Standard FWFT<br />
Read<br />
Port<br />
Depth<br />
Write<br />
Port<br />
Depth<br />
Read<br />
Port<br />
Depth<br />
Write<br />
Port<br />
Depth<br />
Read<br />
Port<br />
Depth<br />
Write<br />
Port<br />
Depth<br />
Read<br />
Port<br />
Depth<br />
4 4 8191 8191 8192 8192 8192 8192 8193 8193<br />
4 8 8191 4095 (1) 8193 4096 (1) 8193 4096 (1) 8195 4097 (1)<br />
4 16 8191 2047 (1) 8195 2048 (1) 8195 2048 (1) 8199 2049 (1)<br />
4 32 8191 1023 (1) 8199 1024 (1) 8199 1024 (1) 8207 1025 (1)<br />
4 64 8191 511 (1) 8207 512 (1) 8207 512 (1) 8223 513 (1)<br />
8 4 4095 8190 4095 (2) 8191 4095 (2) 8191 4096 8192<br />
9 9 4095 4095 4096 4096 4096 4096 4097 4097<br />
9 18 4095 2047 (1) 4097 2048 (1) 4097 2048 (1) 4099 2049 (1)<br />
<strong>UltraScale</strong> <strong>Architecture</strong> <strong>Memory</strong> <strong>Resources</strong> www.xilinx.com<br />
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UG573 (v1.2) February 24, 2015