UltraScale Architecture Memory Resources

Chapter 1: Block RAM Resources
• Separate synchronous set/reset pins independently control the set/reset of the
optional output registers and output latch stages in the block RAM.
• An attribute to configure the block RAM as a common-clock/single-clock FIFO to
eliminate flag latency uncertainty.
• 18, 36, or 72-bit wide block RAM ports can have an individual write enable per byte.
This feature is popular for interfacing to a microprocessor.
• Each block RAM contains optional address sequencing and control circuitry to operate
as a built-in independent-clock FIFO memory. The block RAM can be configured as an
18 Kb or 36 Kb FIFO.
• All inputs are registered with the port clock and have a setup-to-clock timing
specification.
• All outputs have a read function or a read-during-write function, depending on the
state of the write enable (WE) pin. The outputs are available after the clock-to-out
timing interval. The read-during-write outputs have one of three operating modes:
WRITE_FIRST, READ_FIRST, and NO_CHANGE.
• A write operation requires one clock edge.
• A read operation requires one clock edge.
• All output ports are latched or registered (optional). The state of the output port does
not change until the port executes another read or write operation. The default
block RAM output is register mode.
RECOMMENDED: The output datapath has an optional internal pipeline register. Using the register
mode is strongly recommended. This allows a higher clock rate. However, it adds a clock cycle latency
of one.
The block RAM usage rules include:
• The block RAM synchronous output registers (optional) are set or reset (SRVAL) with
RSTREG when DO_REG = 1. The RSTREG_PRIORITY attribute determines if RSTREG has
priority over REGCE. The synchronous output latches are set or reset (SRVAL) with
RSTRAM when DO_REG is 0 or 1.
IMPORTANT: The setup time of the block RAM address and write enable pins must not be violated.
Violating the address setup time (even if write enable is Low) can corrupt the data contents of the
block RAM.
• The block RAM register mode RSTREG requires REGCE = 1 to reset the output DO
register value if the RSTREG_PRIORITY is set to REGCE. The block RAM array data
output latch does not get reset in this mode. The block RAM latch mode RSTRAM
requires the block RAM enable, EN = 1, to reset the output DO latch value.
• There are two block RAM primitives: RAMB36E2 and RAMB18E2.
UltraScale Architecture Memory Resources www.xilinx.com
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UG573 (v1.2) February 24, 2015