UltraScale Architecture Memory Resources

Chapter 2: Built-in FIFO
PROG_FULL_THRESH
PROG_FULL_THRESH is a user-defined threshold that defines when a specified number of
words have been written to the FIFO, and can be used to determine the amount of available
space remaining in the FIFO. When the number of words is more than or equal to
PROG_FULL_THRESH, the PROGFULL signal is asserted. If PROGFULL = 0, the number of
words in the FIFO is less than PROG_FULL_THRESH. Similar to the PROGEMPTY assertion,
the PROGFULL flag conservatively represents the number of words in the FIFO relative to
the PROG_FULL_THRESH setting. Therefore, PROGFULL considers all write operations but
might not immediately update due to read operations synchronization latency. Thus, it can
sometimes present the FIFO as being more full than it actually is.
WRITE_WIDTH
This attribute controls the total data width of the DIN and DINP ports together. Valid values
of WRITE_WIDTH are 4, 9, 18, 36, and 72 (FIFO36E2).
READ_WIDTH
This attribute controls the total data width of the DOUT and DOUTP ports together. Valid
values of READ_WIDTH are 4, 9, 18, 36, and 72 (FIFO36E2).
REGISTER_MODE
UNREGISTERED indicates that the FIFO does not use the block RAM output register.
REGISTERED indicates that the output register is used and that the FIFO controls it such that
the FIFO’s DOUT behaves like an additional FIFO word. This setting does not add any latency
to the DOUT but has an impact on clock-to-out and WRCLK to EMPTY deassertion latency.
DO_PIPELINED indicates that the output register adds an additional pipeline stage to the
DOUT path, with REGCE and RSTREG inputs so that the output register can be controlled.
This setting has an impact on clock-to-out and WRCLK to EMPTY deassertion latency.
CLOCK_DOMAINS
COMMON indicates that the FIFO is a common-clock FIFO, and there is only one clock input
(CLK) or two clock inputs (WRCLK and RDCLK) that are tied to the same clock source (single
clock buffer).
INDEPENDENT indicates that the FIFO has two independent and perhaps asynchronous
clocks (WRCLK and RDCLK) coming from two different clock buffers.
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UG573 (v1.2) February 24, 2015