UltraScale Architecture Memory Resources

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Chapter 1: Block RAM Resources Table 1-14: Block RAM Attributes Table 1-14 lists the RAMB18E2 and RAMB36E2 attributes. All attribute code examples are discussed in Block RAM Initialization in VHDL or Verilog Code, page 44. Further information on using these attributes is available in Additional RAMB18E2 and RAMB36E2 Primitive Design Considerations, page 45. RAMB18E2 and RAMB36E2 Attributes Attributes Values Default Type Description CASCADE_ORDER_A CASCADE_ORDER_B CLOCK_DOMAINS DOA_REG DOB_REG ENADDRENA ENADDRENB INIT_A INIT_B FIRST, MIDDLE, LAST, NONE FIRST, MIDDLE, LAST, NONE INDEPENDENT, COMMON NONE NONE INDEPENDENT String String String 0, 1 1 Decimal 0, 1 1 Decimal FALSE, TRUE FALSE String FALSE, TRUE FALSE String RAMB18E2: 18-bit hex value RAMB36E2: 36-bit hex value RAMB18E2: 18-bit hex value RAMB36E2: 36-bit hex value RAMB18E2: 18'h00000000 RAMB36E2: 36'h00000000 00000000 RAMB18E2: 18'h00000000 RAMB36E2: 36'h00000000 00000000 Hex Hex Specifies the order of the cascaded block RAMs from the bottom to the top of the chain for port A. Specifies the order of the cascaded block RAMs from the bottom to the top of the chain for port B. Either independent clocks connected to port A and B or a single, common clock connected to port A and B. A value of 1 enables the optional output registers of the RAM port A. Applies to all port A outputs in both TDP and SDP memory usage. A value of 1 enables the optional output registers of the RAM port B. Applies to all port B outputs in both TDP and SDP memory usage. Specifies if the address enable pin on port A is enabled. Specifies if the address enable pin on port B is enabled. Specifies the initial value of the port A outputs after configuration. Applies to all port A outputs in both TDP and SDP memory usage. Specifies the initial value of the port B outputs after configuration. Applies to all port B outputs in both TDP and SDP memory usage. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 36 UG573 (v1.2) February 24, 2015
Chapter 1: Block RAM Resources Table 1-14: RAMB18E2: INIT_00 to INIT_3F RAMB36E2: INIT_00 to INIT_7F RAMB18E2: INITP_00 to INITP_07 RAMB36E2: INITP_00 to INITP_0F RDADDRCHANGEA RDADDRCHANGEB A 256-bit hex value A 256-bit hex value READ_WIDTH_A RAMB18E2: 0, 1, 2, 4, 9, 18, 36 (SDP usage) RAMB36E2: 0, 1, 2, 4, 9, 18, 36, 72 (SDP usage) READ_WIDTH_B RSTREG_PRIORITY_A RSTREG_PRIORITY_B SLEEP_ASYNC SRVAL_A RAMB18E2 and RAMB36E2 Attributes (Cont’d) Attributes Values Default Type Description All 0 All 0 Hex Hex FALSE, TRUE FALSE String FALSE, TRUE FALSE String RAMB18E2: 0, 1, 2, 4, 9, 18 RAMB36E2: 0, 1, 2, 4, 9, 18, 36 0 Decimal 0 Decimal RSTREG, REGCE RSTREG String RSTREG, REGCE RSTREG String FALSE, TRUE FALSE String RAMB18E2: 18-bit hex value RAMB36E2: 36-bit hex value RAMB18E2: 18'h00000000 RAMB36E2: 36'h00000000 00000000 Hex Initializes the data content of the block RAM. Initializes the parity content of the block RAM. Specifies if the port A read address compare feature is turned on. Specifies if the port B read address compare feature is turned on. Specifies the data width for read port A, including parity bits. This value must be 0 if port A is not used. Specifies the data width for read port B including parity bits. This value must be 0 if port B is not used. Not used for SDP memory usage. Selects the priority of RESET or CE for the optional output registers. Applies to all port A outputs in both TDP and SDP memory usage. Selects the priority of RESET or CE for the optional output registers. Applies to all port B outputs in both TDP and SDP memory usage. Determines if the SLEEP pin is synchronous or asynchronous to the clock. Specifies the initialization value of the output latches or register when the synchronous reset (RSTREG) is asserted. Applies to all port A outputs in both TDP and SDP memory usage. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 37 UG573 (v1.2) February 24, 2015
Page 1 and 2: UltraScale Architecture Memory Reso
Page 3 and 4: Table of Contents Revision History
Page 5 and 6: Chapter 1 Block RAM Resources Intro
Page 7 and 8: Chapter 1: Block RAM Resources •
Page 9 and 10: Chapter 1: Block RAM Resources •
Page 11 and 12: Chapter 1: Block RAM Resources Tabl
Page 13 and 14: Chapter 1: Block RAM Resources NO_C
Page 15 and 16: Chapter 1: Block RAM Resources Simp
Page 17 and 18: Chapter 1: Block RAM Resources capa
Page 19 and 20: Chapter 1: Block RAM Resources Stan
Page 21 and 22: Chapter 1: Block RAM Resources Data
Page 23 and 24: Chapter 1: Block RAM Resources Byte
Page 25 and 26: Chapter 1: Block RAM Resources Figu
Page 29 and 30: Chapter 1: Block RAM Resources Regi
Page 33 and 34: Chapter 1: Block RAM Resources CASD
Page 35: Chapter 1: Block RAM Resources Tabl
Page 39 and 40: Chapter 1: Block RAM Resources Cont
Page 41 and 42: Chapter 1: Block RAM Resources Read
Page 43 and 44: Chapter 1: Block RAM Resources Opti
Page 45 and 46: Chapter 1: Block RAM Resources Addi
Page 47 and 48: Chapter 1: Block RAM Resources Bloc
Page 49 and 50: Chapter 2 Built-in FIFO Overview Ma
Page 51 and 52: Chapter 2: Built-in FIFO Table 2-1:
Page 59 and 60: Chapter 2: Built-in FIFO Figure 2-3
Page 65 and 66: Chapter 2: Built-in FIFO FIFO18/36
Page 69 and 70: Chapter 2: Built-in FIFO • MIDDLE
Page 71 and 72: Chapter 2: Built-in FIFO FWFT Mode
Page 73 and 74: Chapter 2: Built-in FIFO FIFO might
Page 75 and 76: Chapter 2: Built-in FIFO the status
Page 77 and 78: Chapter 2: Built-in FIFO X-Ref Targ
Page 83 and 84: Chapter 3: Built-in Error Correctio
Page 85 and 86: Chapter 3: Built-in Error Correctio
Page 87 and 88:
Chapter 3: Built-in Error Correctio
Page 89 and 90:
Appendix A Additional Resources and
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