UltraScale Architecture Memory Resources

Chapter 2: Built-in FIFO
Table 2-6:
FIFO18:
CASDOUTP
FIFO36:
CASDOUTP
FIFO18E2 and FIFO36E2 Port Names and Descriptions (Cont’d)
Port Direction Description Configurations
Output
FIFO parity data output bus to next
FIFO when cascading FIFOs serially or
in parallel to extend depth.
CASPRVEMPTY Input Cascaded EMPTY input from previous
FIFO, used for cascading FIFOs serially
to extend depth. Connects to the
CASNXTEMPTY of the previous FIFO.
CASPRVRDEN Output Control output driving the cascaded
RDEN input of the previous FIFO, used
for cascading FIFOs serially to extend
depth. Connects to CASNXTRDEN of
the previous FIFO.
CASNXTRDEN Input Cascaded RDEN input from next FIFO,
used for cascading FIFOs serially to
extend depth. Connects to
CASPRVRDEN of the next FIFO.
CASNXTEMPTY Output Cascaded EMPTY output to next FIFO,
used for cascading FIFOs serially to
extend depth. Connects to
CASPRVEMPTY of the next FIFO.
CASOREGIMUX Input D input to flip-flop that drives the
select line to the cascade multiplexer
before the output registers.
CASOREGIMUXEN Input EN input to flip-flop that drives the
select line to the cascade multiplexer
before the output registers.
CASDOMUX Input D input to flip-flop that drives the
select line to the cascade multiplexer
on the block RAM outputs.
CASDOMUXEN Input EN input to the flip-flop that drives the
select line to the cascade multiplexer
on the block RAM outputs.
Only used when
CASCADE_ORDER = FIRST,
MIDDLE, or PARALLEL.
Only used when
CASCADE_ORDER = MIDDLE or
LAST and cascading FIFOs serially.
Only used when
CASCADE_ORDER = MIDDLE or
LAST and cascading FIFOs serially.
Only used when
CASCADE_ORDER = FIRST or
MIDDLE and cascading FIFOs
serially.
Only used when
CASCADE_ORDER = FIRST or
MIDDLE and cascading FIFOs
serially.
Only used when
REGISTER_MODE = DO_PIPELINED
and
CASCADE_ORDER = PARALLEL.
Only used when
REGISTER_MODE = DO_PIPELINED
and
CASCADE_ORDER = PARALLEL.
Only used when
CASCADE_ORDER = PARALLEL.
Only used when
CASCADE_ORDER = PARALLEL.
Notes:
1. The ports for using the FIFO36E2 in ECC mode are described in Chapter 3, Built-in Error Correction.
2. See block RAM SLEEP pin and attribute descriptions for more information. For the FIFO sleep mode, the assertion and
deassertion of RDEN/WREN requirements deviate from the block RAM rules depending on the clock mode
(independent/common), read/write clock frequency ratios, and other FIFO configurations, such as FWFT and output/pipeline
registers. It is recommended to simulate the design to determine the exact behavior for specific configurations
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UG573 (v1.2) February 24, 2015