UltraScale Architecture Memory Resources

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Chapter 3: Built-in Error Correction • In ECC configuration, the block RAM can be in either READ_FIRST, WRITE_FIRST, and NO_CHANGE mode. See also Address Collision in Chapter 1. UltraScale architecture-based devices have an ECC pipeline mode. This is in addition to the optional registers on the outputs. These registers effectively pipeline the decoder for further improvement in maximum performance (F MAX ) and clock-to-out in latch mode. If turned on, the latency increases by one clock cycle because while the current address is read from the block RAM, the previous address is being decoded. The ECC pipeline register has a user accessible ENABLE control but does not have a reset control. Asserting the block RAM reset pins RSTRAM and RSTREG has no impact on this register, and the previously registered data remains in the register. When using EN_ECC_PIPE = TRUE with the FIFO, the FIFO controller always automatically manages the ECC pipeline register and the associated ECCPIPECE pin. The effective read depth of the FIFO is increase by one word, and the read clock to write flags EMPTY/PROGEMPTY deassertion latency also increase by one. However, the read to DOUT latency does not change. Top-Level View of the Block RAM ECC Architecture Figure 3-1 shows the top-level view of a block RAM in ECC mode. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 84 UG573 (v1.2) February 24, 2015
Chapter 3: Built-in Error Correction X-Ref Target - Figure 3-1 WRADDR[8:0] RDADDR[8:0] DINP[7:0] ECCPARITY[7:0] INJECTSBITERR INJECTDBITERR DIN[63:0] 8 1 1 64 64-bit ECC Encode wraddr 9 rdaddr 9 8 0 8 8 Data In 1 EN_ECC_WRITE 64 DOUT[63:0] DO_REG 0 1 Q DO_REG D EN_ECC_READ 64 64 0 64 1 Data Out 64 EN_ECC_PIPE Q D EN Block RAM 512 x 72 DBITERR SBITERR 0 1 Q DO_REG 0 1 Q D D 1 1 0 1 0 1 1 1 Decode and Correct ECCPIPECE EN_ECC_PIPE DOUTP[7:0] DO_REG 0 1 Q DO_REG D 8 1 0 8 8 EN_ECC_READ Parity Out 8 Q D EN ECCPIPECE EN_ECC_PIPE RDADDRECC[8:0] 0 1 Q D 9 Q D EN Figure 3-1: Top-Level View of Block RAM ECC ECCPIPECE UG573_c3_01_101013 UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 85 UG573 (v1.2) February 24, 2015
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UltraScale Architecture Memory Reso
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Table of Contents Revision History
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Chapter 1 Block RAM Resources Intro
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Chapter 1: Block RAM Resources •
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Chapter 1: Block RAM Resources •
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Chapter 1: Block RAM Resources Tabl
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Chapter 1: Block RAM Resources NO_C
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Chapter 1: Block RAM Resources Simp
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Chapter 1: Block RAM Resources capa
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Chapter 1: Block RAM Resources Stan
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Chapter 1: Block RAM Resources Data
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Chapter 1: Block RAM Resources Byte
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Chapter 1: Block RAM Resources Figu
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Chapter 1: Block RAM Resources Regi
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Page 41 and 42: Chapter 1: Block RAM Resources Read
Page 43 and 44: Chapter 1: Block RAM Resources Opti
Page 45 and 46: Chapter 1: Block RAM Resources Addi
Page 47 and 48: Chapter 1: Block RAM Resources Bloc
Page 49 and 50: Chapter 2 Built-in FIFO Overview Ma
Page 51 and 52: Chapter 2: Built-in FIFO Table 2-1:
Page 59 and 60: Chapter 2: Built-in FIFO Figure 2-3
Page 65 and 66: Chapter 2: Built-in FIFO FIFO18/36
Page 69 and 70: Chapter 2: Built-in FIFO • MIDDLE
Page 71 and 72: Chapter 2: Built-in FIFO FWFT Mode
Page 73 and 74: Chapter 2: Built-in FIFO FIFO might
Page 75 and 76: Chapter 2: Built-in FIFO the status
Page 77 and 78: Chapter 2: Built-in FIFO X-Ref Targ
Page 83: Chapter 3: Built-in Error Correctio
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Page 89 and 90: Appendix A Additional Resources and
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UltraScale Architecture Memory Resources

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