UltraScale Architecture Memory Resources

Chapter 2: Built-in FIFO
• MIDDLE: FIFO is part of a chain of FIFOs cascaded to extend depth. It connects to the
previous FIFO configured as FIRST or MIDDLE and connects to the next FIFO configured
as MIDDLE or LAST.
• LAST: FIFO is the last in a series of FIFOs cascaded to extend depth. It has a normal read
interface, but the write interface is modified to link with the previous FIFO in the chain.
• PARALLEL: FIFO is used in a design where the output data is cascaded in parallel.
FIFO Operations
Reset
IMPORTANT: The reset spec and implementation has been changed completely compared to 7 series
FIFOs. RST is synchronous to WRCLK. To assert RST, it must be asserted for one setup time prior to the
rising edge of WRCLK. RST has an optional inversion at the input.
If RST is asserted, the WRRSTBUSY output asserts immediately after the rising edge of
WRCLK, and remains asserted until the reset operation is complete. Following the assertion
of WRRSTBUSY, the internal reset is synchronized to the RDCLK domain. Upon arrival in the
RDCLK domain, the RDRSTBUSY is asserted, and is held asserted until the resetting of all
RDCLK domain signals is complete, then RDRSTBUSY is deasserted. In common-clock Mode,
this logic is simplified because the clock domain crossing is not required.
Operating Mode
There are two read operating modes in FIFO functions: standard and first-word fall-through
(FWFT). The modes differ in output behavior immediately after the first word is written to a
previously empty FIFO. For more details, see FWFT Mode.
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UG573 (v1.2) February 24, 2015