UltraScale Architecture Memory Resources

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Chapter 2: Built-in FIFO Table 2-7: SRVAL (1) WRCOUNT_TYPE RDCOUNT_TYPE FIFO18: 36 bit hex FIFO36: 72 bit hex RAW_PNTR, SYNC_PNTR, SIMPLE_DATACOUNT, EXTENDED_DATACOUNT RAW_PNTR, SYNC_PNTR, SIMPLE_DATACOUNT, EXTENDED_DATACOUNT 36'h0000000000 72'h0000000000 0000000000 RAW_PNTR RAW_PNTR Specifies the reset value of the FIFO output bus. This is the reset value of both the RAM output latches and the output registers, regardless of the state of REGISTER_MODE. When REGISTER_MODE = DO_PIPELINED, the RSTREG input resets the DOUT output of the FIFO’s output register stage to this value. Otherwise, DOUT is reset by the FIFO’s RST input. Defines the behavior of the WRCOUNT output. WRCOUNT_TYPE can be configured to provide internal FIFO counter information or a count of the FIFO contents. Defines the behavior of the RDCOUNT output. RDCOUNT_TYPE can be configured to provide internal FIFO counter information or a count of the FIFO contents. RSTREG_PRIORITY RSTREG, REGCE RSTREG Only used when REGISTER_MODE = DO_PIPELINED. If set to RSTREG, the RSTREG input resets the output register to SRVAL regardless of the state of the REGCE input. If set to REGCE, the RSTREG input resets the output register to SRVAL only if the REGCE input is 1. CASCADE_ORDER FIFO18E2 and FIFO36E2 Attributes and Descriptions (Cont’d) Attribute Values Default Description NONE, FIRST, MIDDLE, LAST, PARALLEL NONE Notes: 1. The attributes for using the FIFO36E2 in ECC mode are described in Chapter 3, Built-in Error Correction. Defines the FIFO cascade mode (serial or parallel) and cascade order when cascading FIFOs in series. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 64 UG573 (v1.2) February 24, 2015
Chapter 2: Built-in FIFO FIFO18/36 Unused Inputs The unused inputs are shown in Table 2-8. Table 2-8: FIFO18/36 Unused Inputs FIFO18/36 FIFO Attribute Descriptions PROG_EMPTY_THRESH Constant RDCLK 0 WRCLK 0 RDEN 0 WREN 0 REGCLK 0 RSTREG 0 REGCE 1 RST 0 SLEEP 0 CASDOMUX 0 CASOREGIMUX 0 CASDOMUXEN 1 CASOREGIMUXEN 1 INJECTSBITERR 0 INJECTDBITERR 0 PROG_EMPTY_THRESH is a user-defined threshold that defines when a specified number of words have been read from the FIFO. When the number of words is less than or equal to PROG_EMPTY_THRESH, the PROGEMPTY signal is asserted. If PROGEMPTY = 0, the number of words in the FIFO is greater than PROG_EMPTY_THRESH. The PROGEMPTY flag conservatively represents the number of words in the FIFO relative to the PROG_EMPTY_THRESH setting. Therefore, PROGEMPTY considers all read operations but might not immediately update due to write operations synchronization latency. Thus, it can sometimes present the FIFO as more empty than it actually is. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 65 UG573 (v1.2) February 24, 2015
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Table of Contents Revision History
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Chapter 1 Block RAM Resources Intro
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Chapter 1: Block RAM Resources •
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Chapter 1: Block RAM Resources •
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Chapter 1: Block RAM Resources Tabl
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Page 15 and 16: Chapter 1: Block RAM Resources Simp
Page 17 and 18: Chapter 1: Block RAM Resources capa
Page 19 and 20: Chapter 1: Block RAM Resources Stan
Page 21 and 22: Chapter 1: Block RAM Resources Data
Page 23 and 24: Chapter 1: Block RAM Resources Byte
Page 25 and 26: Chapter 1: Block RAM Resources Figu
Page 27 and 28: Chapter 1: Block RAM Resources Tabl
Page 29 and 30: Chapter 1: Block RAM Resources Regi
Page 33 and 34: Chapter 1: Block RAM Resources CASD
Page 39 and 40: Chapter 1: Block RAM Resources Cont
Page 41 and 42: Chapter 1: Block RAM Resources Read
Page 43 and 44: Chapter 1: Block RAM Resources Opti
Page 45 and 46: Chapter 1: Block RAM Resources Addi
Page 47 and 48: Chapter 1: Block RAM Resources Bloc
Page 49 and 50: Chapter 2 Built-in FIFO Overview Ma
Page 51 and 52: Chapter 2: Built-in FIFO Table 2-1:
Page 59 and 60: Chapter 2: Built-in FIFO Figure 2-3
Page 63: Chapter 2: Built-in FIFO Table 2-7:
Page 69 and 70: Chapter 2: Built-in FIFO • MIDDLE
Page 71 and 72: Chapter 2: Built-in FIFO FWFT Mode
Page 73 and 74: Chapter 2: Built-in FIFO FIFO might
Page 75 and 76: Chapter 2: Built-in FIFO the status
Page 77 and 78: Chapter 2: Built-in FIFO X-Ref Targ
Page 83 and 84: Chapter 3: Built-in Error Correctio
Page 89 and 90: Appendix A Additional Resources and
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