UltraScale Architecture Memory Resources

Chapter 1: Block RAM Resources
Optional Output Register On/Off Switch – DOUT[A|B]_REG
This attribute sets the optional pipeline registers at the A/B output of the block RAM
improving the clock-to-out timing. If turned on, this adds an extra cycle of read latency.
When turned off, the block RAM data is read in the same clock cycle, however with a slower
clock-to-out. The valid values are 0 (default) or 1.
Write Width – WRITE_WIDTH_[A|B]
This attribute determines the A/B write port width of the block RAM. The valid values are: 0
(default), 1, 2, 4, 9, 18, 36, and 72 for the RAMB36E2 when used as SDP memory.
Write Mode – WRITE_MODE_[A|B]
This attribute determines the write mode of the A/B input ports. The possible values are
WRITE_FIRST (default), READ_FIRST, and NO_CHANGE. Additional information on the write
modes is in Write Modes, page 11.
SIM_COLLISION_CHECK
This attribute sets the level of collision checking and behavior in the simulation model.
Possible values are ALL (default), GENERATE_X_ONLY, NONE, and WARNING_ONLY.
INIT_FILE
This attribute points to an optional RAM initialization file (initial content). The values are
NONE (default) or a STRING (the file name). For the file format, see the software
documentation.
UltraScale Architecture Memory Resources www.xilinx.com
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UG573 (v1.2) February 24, 2015