UltraScale Architecture Memory Resources

Chapter 1: Block RAM Resources
Additional RAMB18E2 and RAMB36E2 Primitive
Design Considerations
The RAMB18E2 and RAMB36E2 primitives are integral in the block RAM solution.
Optional Output Registers
Optional output registers can be used at either or both A|B output ports of RAMB18E2 and
RAMB36E2. The choice is made using the DO[A|B]_REG attribute. The two independent
clock enable pins are REGCE[A|B]. When using the optional output registers at port [A|B],
assertion of the synchronous set/reset (RSTREG and RSTRAM) pins of ports [A|B] causes the
value specified by the attribute SRVAL to be registered at the output. Figure 1-16 shows an
optional output register.
Independent Read and Write Port Width
IMPORTANT: To specify the port widths using the dual-port mode of the block RAM, designers must use
the READ_WIDTH_[A|B] and WRITE_WIDTH_[A|B] attributes.
These rules should be considered:
• Designing a single-port block RAM requires the port pair widths of one write and one
read to be set (e.g., READ_WIDTH_A and WRITE_WIDTH_A).
• Designing a dual-port block RAM requires all port widths to be set.
• In simple dual-port mode, one side of the ports is fixed while the other side can have a
variable width. The RAMB18E2 has a data port width of up to 36, while the RAMB36E2
has a data port width of up to 72. When using the block RAM as read-only memory,
only the READ_WIDTH_A/B is used.
RAMB18E2 and RAMB36E2 Port Mapping Design Rules
The block RAMs are configurable to various port widths and sizes. Depending on the
configuration, some data pins and address pins are not used. Table 1-7, page 29 through
Table 1-10, page 30 show the pins used in various configurations. In addition to the
information in these tables, these rules are useful to determine the RAMB port connections:
• When using RAMB36E2, if the DIN[A|B] pins are less than 32 bits wide, concatenate
(32 - DIN_BIT_WIDTH) logic zeros to the front of DIN[A|B].
• If the DINP[A|B] pins are less than 4 bits wide, concatenate (4 - DINP_BIT_WIDTH) logic
zeros to the front of DINP[A|B]. DINP[A|B] can be left unconnected when not in use.
UltraScale Architecture Memory Resources www.xilinx.com
Send Feedback
45
UG573 (v1.2) February 24, 2015