UltraScale Architecture Memory Resources

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Chapter 1: Block RAM Resources Data Out Cascade in Pipeline Mode The block RAM pipeline cascade mode is similar to the standard data output cascade mode but allows the application to use the cascade mode at higher frequencies (Figure 1-10). The cascading data output propagates through the regular block RAM output registers because they are used as additional pipeline stages to achieve higher frequencies in this cascade mode. The external CASOREGIMUX pin controls the multiplexer that selects the input to the optional register. Thus, the data from the block RAM below or the current block RAM can be stored into the output register. The input multiplexer always selects DIN to write to the block RAM, the block RAM output multiplexer selects the block RAM output data, or the cascaded data from the block RAM below to write to the register. The final output multiplexer for each of the cascade stages always selects the data from the register for the final output data. All the DO_REG attributes have to be set to TRUE in this case. In this cascading mode, the length of the cascade chain is limited to within one clock region. X-Ref Target - Figure 1-10 DO_REG DIN2 0 1 Block RAM 2 CASOREGIMUXA 0 1 Optional Register 0 0 1 DOUT 1 CASCADE_ORDER = LAST CASDIN DO_REG DIN1 0 1 Block RAM 1 CASOREGIMUXA 0 1 Optional Register 0 0 1 CASDOUT 1 CASCADE_ORDER = MIDDLE CASDIN DO_REG DIN0 0 1 Block RAM 0 0 1 Optional Register 0 0 1 CASDOUT 1 CASCADE_ORDER = FIRST UG573_c1_10_031813 Figure 1-10: Block RAM Cascade – Pipelined Data Out Cascade UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 20 UG573 (v1.2) February 24, 2015
Chapter 1: Block RAM Resources Data in Cascade for a Block RAM Array Matrix (Systolic) Mode The block RAM systolic mode allows an application to write input data or cascaded data into a block RAM (Figure 1-11). At a later cycle, the application can then select to read data from a lower block RAM and write into the next upper block RAM. Data can be read from any dynamically selected block RAM in the cascade chain. The input multiplexer dynamically selects the DIN data or the cascaded data output from the lower block RAM to write to the current block RAM. The block RAM output multiplexer always selects the block RAM output data that is then presented on the data output directly or via the optional register. The DO_REG attribute determines if the optional register is used. In this cascade mode, the length of the cascade chain is limited to within one clock region. X-Ref Target - Figure 1-11 CASCADE_ORDER = LAST DO_REG DIN2 CASDIN 0 1 CASDIMUX Block RAM 2 0 1 Optional Register 0 0 1 DOUT 1 CASCADE_ORDER = MIDDLE DO_REG DIN1 CASDIN 0 1 CASDIMUX Block RAM 1 0 1 Optional Register 0 0 1 CASDOUT 1 CASCADE_ORDER = FIRST DO_REG DIN0 0 1 Block RAM 0 0 1 Optional Register 0 0 1 CASDOUT 1 UG573_c1_11_061313 Figure 1-11: Block RAM Cascade – Arrayed (Systolic) Data in Cascade UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 21 UG573 (v1.2) February 24, 2015
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Page 3 and 4: Table of Contents Revision History
Page 5 and 6: Chapter 1 Block RAM Resources Intro
Page 7 and 8: Chapter 1: Block RAM Resources •
Page 9 and 10: Chapter 1: Block RAM Resources •
Page 11 and 12: Chapter 1: Block RAM Resources Tabl
Page 13 and 14: Chapter 1: Block RAM Resources NO_C
Page 15 and 16: Chapter 1: Block RAM Resources Simp
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Page 41 and 42: Chapter 1: Block RAM Resources Read
Page 43 and 44: Chapter 1: Block RAM Resources Opti
Page 45 and 46: Chapter 1: Block RAM Resources Addi
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Page 49 and 50: Chapter 2 Built-in FIFO Overview Ma
Page 51 and 52: Chapter 2: Built-in FIFO Table 2-1:
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Chapter 2: Built-in FIFO FWFT Mode
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Chapter 2: Built-in FIFO FIFO might
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Chapter 2: Built-in FIFO the status
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Chapter 2: Built-in FIFO X-Ref Targ
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Chapter 2: Built-in FIFO Figure 2-1
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Chapter 2: Built-in FIFO Figure 2-1
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Chapter 3: Built-in Error Correctio
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Appendix A Additional Resources and
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