UltraScale Architecture Memory Resources

Chapter 1: Block RAM Resources
Inverting Control Pins
For each port, the eight control pins (CLK, EN, RSTREG, and RSTRAM) each have an
individual inversion option. EN, RSTREG, and RSTRAM control signals can be configured as
active-High or Low, and the clock can be active on a rising or falling edge (active-High on
rising edge by default), without requiring other logic resources.
RAMB18/36 Unused Inputs
The unused inputs are shown in Table 1-12.
Table 1-12:
RAMB18/36 Unused Inputs
RAMB18/36 Constant Comments
ADDRENA 1
ADDRENB 1
CLKARDCLK 0
CLKBRDCLK 0
CLKAWRCLK 0
CLKBWRCLK 0
ENARDEN 0
ENBWREN 0
REGCEAREGCE
REGCEB
REGCLKARDRCLK 0
REGCLKB 0
RSTREGARSTREG 0
RSTREGB 0
RSTRAMARSTRAM 0
RSTRAMB 0
RSTRAMARSTRAM 0
RSTRAMB 0
SLEEP 0
WEA
WEBWE
CASDOMUXA 0
CASDOMUXB 0
1
1
1
1
Xilinx recommends setting to 0 when DOA_REG = 0 for
power saving
Xilinx recommends setting to 0 when DOB_REG = 0 for
power saving
TDP: When not using port A for write,
(WRITE_WIDTH_A = 0), WEA must be connected to 0
TDP: When not using port B for write (WRITE_WIDTH_B=0),
WEB must be connected to 0
UltraScale Architecture Memory Resources www.xilinx.com
Send Feedback
34
UG573 (v1.2) February 24, 2015