UltraScale Architecture Memory Resources

Chapter 2: Built-in FIFO
X-Ref Target - Figure 2-8
Figure 2-8:
Deassertion and Assertion Latencies of FULL and PROGFULL
for Independent-Clock FIFO
Table 2-11:
The programmable flags in Figure 2-7 and Figure 2-8 are asserted and deasserted based on
their threshold settings and there is no dependency or relationship to the EMPTY/FULL
flags.
Common-clock FIFO
Assertion (1)
Deassertion
Standard FIFO (2)
Deassertion
FWFT FIFO (2)
EMPTY 0 RDCLK 0 WRCLK (3) 1 WRCLK (3)
PROGEMPTY 1 RDCLK 1 WRCLK 1 WRCLK
FULL 0 WRCLK 0 RDCLK 0 RDCLK
PROGFULL 1 WRCLK 1 RDCLK 1 RDCLK
Notes:
1. Assertion latency is from the rising edge of the RD/WR with the RD/WR operation enabled if the operation caused
the FIFO to go EMPTY (PROGEMPTY) or FULL (PROGFULL). A latency of zero indicates that the flag asserts
immediately following the rising edge of the clock, and a latency of one indicates that one extra rising clock edge
is required.
2. Deassertion latency is from the rising edge of the clock when the operation is enabled to the deassertion of the
flag when the FIFO is no longer EMPTY (PROGEMPTY) or FULL (PROGFULL). A latency of zero indicates that the flag
deasserts immediately following the rising edge of the clock, and a latency of one indicates that one extra rising
clock edge is required.
3. Registered mode adds one RDCLK clock cycle.
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UG573 (v1.2) February 24, 2015