UltraScale Architecture Memory Resources

Chapter 2: Built-in FIFO
• CASPRVEMPTY input: The CASPRVEMPTY input of a cascaded FIFO with
CASCADE_ORDER = MIDDLE or LAST is the cascaded EMPTY input from the previous
FIFO in the chain to the current FIFO. CASPRVEMPTY connects to the CASNXTEMPTY
output on the previous FIFO in the chain (configured with CASCADE_ORDER = FIRST or
MIDDLE). When CASPRVEMPTY = 0, the current FIFO knows that it can transfer a word
of data from the previous FIFO to the current FIFO.
• CASPRVRDEN output: The CASPRVRDEN output of a cascaded FIFO with
CASCADE_ORDER = MIDDLE or LAST is the cascaded RDEN output from the current
FIFO to the previous FIFO in the chain. CASPRVRDEN connects to the CASNXTRDEN
input on the previous FIFO in the chain (configured with CASCADE_ORDER = FIRST or
MIDDLE), indicating when to read from the previous FIFO as part of a data word
transfer between the two FIFOs.
• CASNXTRDEN input: The CASNXTRDEN input of a cascaded FIFO with
CASCADE_ORDER = FIRST or MIDDLE is the cascade RDEN input from the next FIFO to
the current FIFO in the chain. CASNXTRDEN connects to the CASPRVRDEN output from
the next FIFO in the chain (configured with CASCADE_ORDER = MIDDLE or LAST).
Cascading in Parallel
FIFOs can be cascaded in parallel mode based on the block RAM standard/pipelined data
out cascade mode utilizing the same multiplexer pins available in the block RAM mode. This
cascading mode is available in both FIFO18E2 and FIFO36E2. The parallel mode requires
additional user logic and it is the application’s responsibility to provide the appropriate
logic for the read and write interfaces for each FIFO in the cascade chain as well as the
multiplexer control.
When CASCADE_ORDER = PARALLEL, there are four additional FIFO inputs available that are
used to control the cascade data multiplexers for that FIFO. These inputs are identical to the
equivalent block RAM pins CASOREGIMUX and CASOREGIMUXEN (for controlling the
pipeline register cascade multiplexer), and CASDOMUX and CASDOMUXEN (for controlling
the output cascade multiplexer). In this mode, the special serial cascade control pins are not
available (CASNXTEMPTY, CASPRVEMPTY, CASNXTRDEN, CASPRVRDEN).
IMPORTANT: CASCADE_ORDER must be set to PARALLEL for the cascade input multiplexers to be
available.
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UG573 (v1.2) February 24, 2015