UltraScale Architecture Memory Resources

More documents

Recommendations

Info

Chapter 2: Built-in FIFO X-Ref Target - Figure 2-8 Figure 2-8: Deassertion and Assertion Latencies of FULL and PROGFULL for Independent-Clock FIFO Table 2-11: The programmable flags in Figure 2-7 and Figure 2-8 are asserted and deasserted based on their threshold settings and there is no dependency or relationship to the EMPTY/FULL flags. Common-clock FIFO Assertion (1) Deassertion Standard FIFO (2) Deassertion FWFT FIFO (2) EMPTY 0 RDCLK 0 WRCLK (3) 1 WRCLK (3) PROGEMPTY 1 RDCLK 1 WRCLK 1 WRCLK FULL 0 WRCLK 0 RDCLK 0 RDCLK PROGFULL 1 WRCLK 1 RDCLK 1 RDCLK Notes: 1. Assertion latency is from the rising edge of the RD/WR with the RD/WR operation enabled if the operation caused the FIFO to go EMPTY (PROGEMPTY) or FULL (PROGFULL). A latency of zero indicates that the flag asserts immediately following the rising edge of the clock, and a latency of one indicates that one extra rising clock edge is required. 2. Deassertion latency is from the rising edge of the clock when the operation is enabled to the deassertion of the flag when the FIFO is no longer EMPTY (PROGEMPTY) or FULL (PROGFULL). A latency of zero indicates that the flag deasserts immediately following the rising edge of the clock, and a latency of one indicates that one extra rising clock edge is required. 3. Registered mode adds one RDCLK clock cycle. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 76 UG573 (v1.2) February 24, 2015
Chapter 2: Built-in FIFO X-Ref Target - Figure 2-9 Figure 2-9: Deassertion and Assertion Latencies of EMPTY and PROGEMPTY for Common-Clock FIFO X-Ref Target - Figure 2-10 Figure 2-10: Deassertion and Assertion Latencies of FULL and PROGFULL for Common-Clock FIFO The programmable flags in Figure 2-9 and Figure 2-10 are asserted and deasserted based on their threshold settings and there is no dependency or relationship to the EMPTY/FULL flags. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 77 UG573 (v1.2) February 24, 2015
Page 1 and 2:
UltraScale Architecture Memory Reso
Page 3 and 4:
Table of Contents Revision History
Page 5 and 6:
Chapter 1 Block RAM Resources Intro
Page 7 and 8:
Chapter 1: Block RAM Resources •
Page 9 and 10:
Chapter 1: Block RAM Resources •
Page 11 and 12:
Chapter 1: Block RAM Resources Tabl
Page 13 and 14:
Chapter 1: Block RAM Resources NO_C
Page 15 and 16:
Chapter 1: Block RAM Resources Simp
Page 17 and 18:
Chapter 1: Block RAM Resources capa
Page 19 and 20:
Chapter 1: Block RAM Resources Stan
Page 21 and 22:
Chapter 1: Block RAM Resources Data
Page 23 and 24:
Chapter 1: Block RAM Resources Byte
Page 25 and 26: Chapter 1: Block RAM Resources Figu
Page 27 and 28: Chapter 1: Block RAM Resources Tabl
Page 29 and 30: Chapter 1: Block RAM Resources Regi
Page 33 and 34: Chapter 1: Block RAM Resources CASD
Page 39 and 40: Chapter 1: Block RAM Resources Cont
Page 41 and 42: Chapter 1: Block RAM Resources Read
Page 43 and 44: Chapter 1: Block RAM Resources Opti
Page 45 and 46: Chapter 1: Block RAM Resources Addi
Page 47 and 48: Chapter 1: Block RAM Resources Bloc
Page 49 and 50: Chapter 2 Built-in FIFO Overview Ma
Page 51 and 52: Chapter 2: Built-in FIFO Table 2-1:
Page 59 and 60: Chapter 2: Built-in FIFO Figure 2-3
Page 65 and 66: Chapter 2: Built-in FIFO FIFO18/36
Page 69 and 70: Chapter 2: Built-in FIFO • MIDDLE
Page 71 and 72: Chapter 2: Built-in FIFO FWFT Mode
Page 73 and 74: Chapter 2: Built-in FIFO FIFO might
Page 75: Chapter 2: Built-in FIFO the status
Page 83 and 84: Chapter 3: Built-in Error Correctio
Page 89 and 90: Appendix A Additional Resources and
show all

UltraScale Architecture Memory Resources

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?