UltraScale Architecture Memory Resources

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Chapter 2: Built-in FIFO Cascading FIFOs Serially and in Parallel to Extend Depth Cascading Serially UltraScale architecture-based devices have built-in support for cascading FIFOs in series to extend depth without requiring logic resources. Dedicating routing and logic have been added to make this cascading mode available in hardware. Cascading FIFOs in series to expand depth is supported for FIFO18E2 primitives and for FIFO36E2 primitives, and two or more FIFOs can be cascaded up to a full column with some limitations (e.g., a PCIe® block interrupting the column). When cascading FIFOs serially, the first FIFO (the FIFO with the write side interface) must have CASCADE_ORDER = FIRST, the last FIFO (the one with the read interface) must have CASCADE_ORDER = LAST, and all other FIFOs in the chain must have CASCADE_ORDER = MIDDLE. FIFOs with a CASCADE_ORDER of FIRST or MIDDLE must be configured with FIRST_WORD_FALL_THROUGH = TRUE. The LAST FIFO in the chain can be in FWFT or standard mode. The FIFO control logic handles all the handshaking between the blocks and all the read and write interfaces. However, the RDCLK and WRCLK pins for all of the FIFOs in the chain must be connected in a specific way. The WRCLK input of the first FIFO should always use the user’s WRCLK, the RDCLK input of the last FIFO should always use the user’s RDCLK, and all other clock inputs should be connected to the faster of the two clocks. When both the WRCLK and RDCLK of a particular FIFO primitive is connected to the same clock input (same clock buffer source), the FIFO can be configured as a common clock FIFO to reduce the latencies through the FIFOs. The FIFOs can be configured in REGISTERED or UNREGISTERED mode. The REGISTERED mode provides maximum performance at the expense of increased latency for the WRCLK and RDCLK flag deassertion. If resetting the FIFO is required, the RST pins of the FIFOs must be connected by the application (tied to a single reset net). The FIFO control logic does not automatically handle the reset flags RDRSTBUSY and WRRSTBUSY, and therefore the application must monitor those if needed (e.g., ORing them). UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 78 UG573 (v1.2) February 24, 2015
Chapter 2: Built-in FIFO Figure 2-11 shows a serial cascading example of three FIFOs. X-Ref Target - Figure 2-11 CASCADE_ORDER = LAST REGISTERED CASDIN BRAM2 0 1 Optional Register 0 0 1 DOUT 1 FIFO Read Interface CASCADE_ORDER = MIDDLE REGISTERED CASDIN BRAM1 0 1 Optional Register 0 0 1 CASDOUT 1 CASCADE_ORDER = FIRST REGISTERED DIN0 FIFO Write Interface BRAM0 0 1 Optional Register 0 0 1 CASDOUT 1 UG573_c2_05_031513 Figure 2-11: FIFO Serial Cascade IMPORTANT: In serial cascade mode, the multiplexer control signals are not accessible and are automatically configured. Aside from the dedicated data cascading pins CASDIN, CASDINP, CASDOUT, and CASDOUTP, the FIFO has four additional control pins to support serial cascading. These pins must be connected as follows: • CASNXTEMPTY output: The CASNXTEMPTY output of a cascaded FIFO with CASCADE_ORDER = FIRST or MIDDLE is the cascaded EMPTY output from the current FIFO to the next in the chain. CASNXTEMPTY connects to the CASPRVEMPTY input on the next FIFO in the chain (configured with CASCADE_ORDER = MIDDLE or LAST), allowing the next FIFO to be aware of when this FIFO is not EMPTY and available for reading. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 79 UG573 (v1.2) February 24, 2015
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Table of Contents Revision History
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Chapter 1 Block RAM Resources Intro
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Chapter 1: Block RAM Resources •
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Chapter 1: Block RAM Resources •
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Chapter 1: Block RAM Resources Tabl
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Chapter 1: Block RAM Resources NO_C
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Chapter 1: Block RAM Resources Simp
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Chapter 1: Block RAM Resources Data
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Chapter 1: Block RAM Resources Byte
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Chapter 1: Block RAM Resources Figu
Page 27 and 28: Chapter 1: Block RAM Resources Tabl
Page 29 and 30: Chapter 1: Block RAM Resources Regi
Page 33 and 34: Chapter 1: Block RAM Resources CASD
Page 39 and 40: Chapter 1: Block RAM Resources Cont
Page 41 and 42: Chapter 1: Block RAM Resources Read
Page 43 and 44: Chapter 1: Block RAM Resources Opti
Page 45 and 46: Chapter 1: Block RAM Resources Addi
Page 47 and 48: Chapter 1: Block RAM Resources Bloc
Page 49 and 50: Chapter 2 Built-in FIFO Overview Ma
Page 51 and 52: Chapter 2: Built-in FIFO Table 2-1:
Page 59 and 60: Chapter 2: Built-in FIFO Figure 2-3
Page 65 and 66: Chapter 2: Built-in FIFO FIFO18/36
Page 69 and 70: Chapter 2: Built-in FIFO • MIDDLE
Page 71 and 72: Chapter 2: Built-in FIFO FWFT Mode
Page 73 and 74: Chapter 2: Built-in FIFO FIFO might
Page 75 and 76: Chapter 2: Built-in FIFO the status
Page 77: Chapter 2: Built-in FIFO X-Ref Targ
Page 81 and 82: Chapter 2: Built-in FIFO Figure 2-1
Page 83 and 84: Chapter 3: Built-in Error Correctio
Page 89 and 90: Appendix A Additional Resources and
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UltraScale Architecture Memory Resources

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