UltraScale Architecture Memory Resources

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Chapter 2: Built-in FIFO Table 2-6: FIFO Port Descriptions and Attributes Table 2-3 lists the FIFO I/O port names and descriptions. FIFO18E2 and FIFO36E2 Port Names and Descriptions Port Direction Description Configurations PROGEMPTY Output Programmable flag to indicate the FIFO is almost empty (contains less than or equal to the number of words specified by PROG_EMPTY_THRESH). Synchronous to RDCLK. PROGFULL Output Programmable flag to indicate the FIFO is almost full (contains greater than or equal to the number of words specified by PROG_FULL_THRESH). Synchronous to WRCLK. FIFO18: DIN FIFO36: DIN FIFO18: DINP FIFO36: DINP FIFO18: DOUT FIFO36: DOUT FIFO18: DOUTP FIFO36: DOUTP Input Input Output Output FIFO data input bus. Synchronous to WRCLK. FIFO parity input bus. Synchronous to WRCLK. FIFO data output bus. Synchronous to RDCLK. FIFO parity output bus. Synchronous to RDCLK. EMPTY Output Active-High flag to indicate when the FIFO is empty. Synchronous to RDCLK. FULL Output Active-High flag to indicate when the FIFO is full. Synchronous to WRCLK. All configurations. Controlled by PROG_EMPTY_THRESH. All configurations. Controlled by PROG_FULL_THRESH. All configurations, width controlled by WRITE_WIDTH. All configurations, width controlled by WRITE_WIDTH. All configurations, width controlled by READ_WIDTH. All configurations, width controlled by READ_WIDTH. All configurations. All configurations. RDCLK Input Read clock. All configurations. FIFO18: RDCOUNT FIFO36: RDCOUNT Output Output of either the internal FIFO read pointer, or a count of the number of words in the FIFO. Synchronous to RDCLK. RDEN Input Active-High read enable relative to RDCLK. RDERR Output Indicates that a read operation failed due to the FIFO being EMPTY, or FIFO in a reset condition. Synchronous to RDCLK. All configurations, output value controlled by RDCOUNT_TYPE. All configurations. All configurations. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 60 UG573 (v1.2) February 24, 2015
Chapter 2: Built-in FIFO Table 2-6: RDRSTBUSY Output Active-High indicator that the FIFO is currently in a reset state. Synchronous to RDCLK. REGCE Input Active-High enable for output register stage relative to RDCLK. RST Input Active-High synchronous reset. Synchronous to WRCLK. RSTREG Input Active-High enable for output register reset relative to RDCLK. SLEEP (2) Input Dynamic shutdown power saving. If SLEEP is High, the block RAM memory array is in power-saving mode. Indicates that the RDCLK domain FIFO logic is currently in a reset state. Any attempt to perform a read operation while RDRSTBUSY = 1 causes a RDERR. Only when REGISTER_MODE = DO_PIPELINED. RST input. Must be synchronous to the WRCLK domain. Only when REGISTER_MODE = DO_PIPELINED. All configurations. WRCLK Input Write clock. All configurations. FIFO18: WRCOUNT FIFO36: WRCOUNT Output Output of either the internal FIFO write pointer, or a count of the number of words in the FIFO. Synchronous to WRCLK. WREN Input Active-High write enable relative to RDCLK. WRERR Output Indicates that a write operation failed due to the FIFO being FULL, or FIFO in a reset condition. Synchronous to WRCLK. WRRSTBUSY Output Active-High indicator that the FIFO is currently in a reset state. Synchronous to WRCLK. FIFO18: CASDIN FIFO36: CASDIN FIFO18: CASDINP FIFO36: CASDINP FIFO18: CASDOUT FIFO36: CASDOUT FIFO18E2 and FIFO36E2 Port Names and Descriptions (Cont’d) Port Direction Description Configurations Input Input Output FIFO data input bus from previous FIFO when cascading FIFOs serially or in parallel to extend depth. FIFO parity data input bus from previous FIFO when cascading FIFOs serially or in parallel to extend depth. FIFO data output bus to next FIFO when cascading FIFOs serially or in parallel to extend depth. All configurations, output value controlled by WRCOUNT_TYPE. All configurations. All configurations. Indicates that the WRCLK domain FIFO logic is currently in a reset state. Any attempt to perform a write operation while WRRSTBUSY = 1 causes a WRERR. Only used when CASCADE_ORDER = MIDDLE, LAST, or PARALLEL. Only used when CASCADE_ORDER = MIDDLE, LAST, or PARALLEL. Only used when CASCADE_ORDER = FIRST, MIDDLE, or PARALLEL. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 61 UG573 (v1.2) February 24, 2015
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UltraScale Architecture Memory Reso
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Table of Contents Revision History
Page 5 and 6:
Chapter 1 Block RAM Resources Intro
Page 7 and 8:
Chapter 1: Block RAM Resources •
Page 9 and 10: Chapter 1: Block RAM Resources •
Page 11 and 12: Chapter 1: Block RAM Resources Tabl
Page 13 and 14: Chapter 1: Block RAM Resources NO_C
Page 15 and 16: Chapter 1: Block RAM Resources Simp
Page 17 and 18: Chapter 1: Block RAM Resources capa
Page 19 and 20: Chapter 1: Block RAM Resources Stan
Page 21 and 22: Chapter 1: Block RAM Resources Data
Page 23 and 24: Chapter 1: Block RAM Resources Byte
Page 25 and 26: Chapter 1: Block RAM Resources Figu
Page 29 and 30: Chapter 1: Block RAM Resources Regi
Page 33 and 34: Chapter 1: Block RAM Resources CASD
Page 39 and 40: Chapter 1: Block RAM Resources Cont
Page 41 and 42: Chapter 1: Block RAM Resources Read
Page 43 and 44: Chapter 1: Block RAM Resources Opti
Page 45 and 46: Chapter 1: Block RAM Resources Addi
Page 47 and 48: Chapter 1: Block RAM Resources Bloc
Page 49 and 50: Chapter 2 Built-in FIFO Overview Ma
Page 51 and 52: Chapter 2: Built-in FIFO Table 2-1:
Page 59: Chapter 2: Built-in FIFO Figure 2-3
Page 65 and 66: Chapter 2: Built-in FIFO FIFO18/36
Page 69 and 70: Chapter 2: Built-in FIFO • MIDDLE
Page 71 and 72: Chapter 2: Built-in FIFO FWFT Mode
Page 73 and 74: Chapter 2: Built-in FIFO FIFO might
Page 75 and 76: Chapter 2: Built-in FIFO the status
Page 77 and 78: Chapter 2: Built-in FIFO X-Ref Targ
Page 79 and 80: Chapter 2: Built-in FIFO Figure 2-1
Page 81 and 82: Chapter 2: Built-in FIFO Figure 2-1
Page 83 and 84: Chapter 3: Built-in Error Correctio
Page 89 and 90: Appendix A Additional Resources and
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