Processor Local Bus Functional Model Toolkit User's Manual

idges, a PLB to OPB bridge which is a slave on the PLB and a master on the OPB and an OPB to
PLB bridge which is a slave on the OPB and a master on the PLB. OPB peripherals may also
comprise DMA peripherals.
The device control register (DCR) bus is used primarily for accessing status and control registers
within the various PLB and OPB masters and slaves. It is meant to off-load the PLB from the lower
performance status and control read and write transfers. The DCR bus architecture allows data
transfers among OPB peripherals to occur independently from, and concurrent with, data transfers
between the processor and memory, or among other PLB devices.
The toolkit allows users to initiate PLB master cycles and provide PLB slave responses through a bus
functional language which is parameterized according to the architectural specification. Data
checking and bus protocol monitoring also provide a way for users to automate the verification of PLB
designs under development. Source files in ASCII format are distributed with the toolkit, which include
behavioral models, programs, and documentation.
1.1 PLB Toolkit Features
PLB toolkit features:
• Unit and subsystem level simulation of logic designs which comply with PLB architecture
specifications.
• VHDL and verilog source model solutions with simulator independence.
• Bus functional command definition which generates and responds to different transaction types
with varying delays.
• Bus functional compiler which generates model initialization files from bus functional commands.
• Bus protocol checking through the use of general purpose bus monitors.
• Read and write data checking in masters and slaves.
• Model inter-communication bus for event and transaction synchronization.
• Enables peripheral developers to verify and debug designs to assure bus compliance.
• Faster simulation run-times than PPC BFM or FFM to generate bus traffic.
• Allows ‘what if’ simulation scenarios using different master and slave configurations.
• Flexible and user-friendly bus functional language (BFL) for quick generation of a variety of bus
transactions.
• Hierarchical solution to verification.
1.2 PLB Features
The PLB model toolkit enables the user to simulate the following PLB features.
• Separate address bus, read data bus and write data bus for each bus master. Shared address bus,
read data bus, and write data bus for all bus slaves.
2 Processor Local Bus Functional Model Toolkit Version 4.9.2