Processor Local Bus Functional Model Toolkit User's Manual

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set_device (path=/plb_complex/plb_slave0,device_type=plb_slave) -- Initialize device 0 mem_init(addr=00000000,data=00010203) mem_init(addr=00000004,data=04050607) mem_init(addr=00000008,data=08090a0b) mem_init(addr=0000000c,data=0c0d0e0f) write_response(aack_delay=0,dack_delay=0) mem_check(level=0,addr=00000000,data=00010203) mem_check(level=0,addr=00000004,data=04050607) mem_check(level=0,addr=00000008,data=08090a0b) mem_check(level=0,addr=0000000c,data=0c0d0e0f) 66 Processor Local Bus Functional Model Toolkit Version 4.9.2
7.9 Four-word Line Read Followed By Four-word Line Write Transfers Figure 16 shows the operation of a four-word line read followed immediately by a four-word line write on the PLB. Cycle SYS_plbClk Transfer Qualifiers Mn_request Mn_priority(0:1) Mn_busLock Mn_RNW Mn_BE(0:3) Mn_size(0:3) Mn_type(0:2) Mn_abort Mn_ABus(0:31) PLB_PAValid Sl_addrAck Write Data Bus Mn_wrDBus(0:31) Sl_wrDAck Sl_wrComp Mn_wrBurst Read Data Bus Sl_rdDBus(0:31) Sl_rdWdAddr(0:3) Sl_rdDAck Sl_rdComp Mn_rdBurst 0001 0001 000 000 A1 A2 Figure 16. Four Word Line Read followed by Four Word Line Write set_device (path=/plb_complex/plb_master0,device_type=plb_master) mem_init(addr=00000000,data=00010203) mem_init(addr=00000004,data=04050607) mem_init(addr=00000008,data=08090a0b) mem_init(addr=0000000c,data=0c0d0e0f) mem_init(addr=00000010,data=10111213) mem_init(addr=00000014,data=14151617) mem_init(addr=00000018,data=18191a1b) 0 1 2 3 4 5 6 7 8 9 0000 0000 Next Read AValid Next Write AValid D0(A2) D1(A2) D2(A2) D3(A2) W0 W1 W2 W3 0000 0001 0010 0011 0000 0000 Version 4.9.2 PLB Bus Timing 67
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Processor Local Bus Functional Mode
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Patents and Trademarks IBM may have
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Command Modes . . . . . . . . . . .
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PLB_MnTimeout . . . . . . . . . . .
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x Processor Local Bus Functional Mo
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xii Processor Local Bus Functional
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Device Control Register Bus Toolkit
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idges, a PLB to OPB bridge which is
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1.3 PLB Implementation The PLB impl
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2.3 VHDL/Verilog Files The followin
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This HDL file is a wrapper which in
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3.2 Instantiating PLB Slave Designs
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Chapter 4. PLB Bus Functional Compi
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Chapter 5. PLB Bus Models The toolk
Page 30 and 31: 5.2 PLB Master Model The PLB master
Page 32 and 33: When the decode unit issues a bus r
Page 34 and 35: 5.2.6 Conversion Cycles with Differ
Page 36 and 37: 5.3 PLB Slave Model PLB slaves resp
Page 38 and 39: This response mode allows the user
Page 40 and 41: 5.3.6 Internal Slave Memory Checkin
Page 42 and 43: PLB Bus Mn_request Mn_priority(0:1)
Page 44 and 45: 6.2.1 Set_Alias () Command The set_
Page 46 and 47: • * size0_min/max = [integer] def
Page 48 and 49: These parameters specify the range
Page 50 and 51: This parameter specifies the mode i
Page 52 and 53: This parameter specifies the data w
Page 54 and 55: 6.3.11 Compare () Command The compa
Page 56 and 57: 6.4.1 Configure () Command The conf
Page 58 and 59: 6.4.1.2 Automatic Command Mode Conf
Page 60 and 61: This parameter specifies the seed t
Page 62 and 63: 6.4.5 Mem_Check () Command The mem_
Page 64 and 65: configure(SLAVE3_ADDR_HI_0=000FFFFF
Page 66 and 67: • * level = [integer: range 0 to
Page 68 and 69: send(level=0) set_device (path=/plb
Page 70 and 71: 7.3 Transfer Abort Figure 10 shows
Page 72 and 73: send(level=0) set_device (path=/plb
Page 74 and 75: write(addr=0000000c,size=0000,be=11
Page 76 and 77: write(addr=0000000c,size=0000,be=11
Page 78 and 79: mem_init(addr=00000000,data=0001020
Page 82 and 83: mem_init(addr=0000001c,data=1c1d1e1
Page 84 and 85: 8.5 Signal Summary Table Table 1 pr
Page 86 and 87: Synch_in Synch_out 8.6 Master Inter
Page 88 and 89: An error message is issued if the M
Page 90 and 91: An error message is issued when a m
Page 92 and 93: • Error 1.16.4 An error message i
Page 94 and 95: An error message is issued when PLB
Page 96 and 97: 8.7.4 Sln_wait The following error
Page 102 and 103: When PLB_PAValid or PLB_SAValid is
Page 104 and 105: 8.8.9 PLB_rdBurst The following err
Page 106 and 107: 8.9.2 PLB_MnRdBTerm The following e
Page 108 and 109: PLB master mode 16 PLB master model
Page 110: © International Business Machines
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Processor Local Bus Functional Model Toolkit User's Manual

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