Processor Local Bus Functional Model Toolkit User's Manual

5.2.6 Conversion Cycles with Different PLB Device Sizes
The PLB master model can be configured to be a 32-bit, 64-bit, or 128-bit device. When the PLB
master model receives a PLB_MnSSize with PLB_MnAddrAck which represents a slave that is
smaller than the configured PLB master size (Mn_Msize(0:1)), the PLB master will automatically
generate additional cycles to complete the original requested transaction. These additional cycles can
be referred to as “conversion cycles.” For example, a 64-bit PLB master will always generate one
additional cycle when a 32-bit slave responds to a single transfer (M_Size=”0000”) read or write
cycle. For line transfers, the PLB master completes the request when the appropriate number of
words have been transferred as determined by the transaction width (MSize/SSize) and the transfer
size (M_Size). See PLB architecture specifications for details on different device widths.
5.2.7 General Purpose and Branch Processor Registers
The PLB master model contains 32 general purpose registers (R0-31), a 32-bit synchronization
register (SR) and a 32-bit condition register (CR). These registers can be used by the programmer to
implement algorithms or conditions which affect the way in which the PLB master executes
commands.
The condition register is updated during ‘compare’ instructions. It provides a mechanism for testing
and branching. The bits of the Condition Register are grouped into eight 4-bit fields, named CR Field
0 (CR0)..., CR Field 7 (CR7). Instructions are provided to perform logical operations on individual CR
bits and to test individual CR bits. The bits of the CR “fields” are interpreted as follows:
- bit 0: Negative (LT) The result is negative.
- bit 1: Positive (GT) The result is positive.
- bit 2: Zero (EQ) The result is zero.
- bit 3: undefined
The synchronization register latches the Synch_in input. It can subsequently be referenced or reset
using an ALU or move instruction.
5.2.8 ALU Instructions
The following instructions are available for arithmetic operations: (a detailed description is provided in
“PLB Master Commands” on page 30)
– Add()
– Sub()
– And
– Or
– Shift_Left
– Shift_Right
– Compare()
20 Processor Local Bus Functional Model Toolkit Version 4.9.2