Processor Local Bus Functional Model Toolkit User's Manual

This parameter specifies the address incrementation order for the slave during line transfers. The
valid modes are sequential and target word first. When this parameter is used in the configuration
statement of the slave, the rdWord_mode will be constant for the entire simulation session.
• * fixed_burst_mode = [1 bit] 0=disabled, 1=enabled default:0
This parameter configures the slave to automatically assert the Sl_rd/wrBterm signal when a fixed
length burst cycle is in progress and the corresponding number of data transfer has occurred on
the bus.
• * wait_disable = [1 bit] 0=enabled,1=disabled default:0
This parameter specifies if the Sl_wait signal can be asserted. When this parameter is used in the
configuration statement of the slave, the wait_disable will be constant for the entire simulation
session.
• * wait_mode = [1 bit] 0=assert on address,1=delay mode default:0
This parameter specifies how the Sl_wait signal is asserted. When assert on address mode is
used, the slave will assert Sl_wait whenever the PLB_Abus is within the slave address range.
When delay mode is used, Sl_wait will be asserted based on both an address match and the wait
parameter of the read/write response commands.
• * read_addr_pipeline_disable = [1 bit] 0=SAValid recognized,1=SAValid ignored default:0
This parameter specifies whether the PLB core secondary address valid control signal is
recognized by the PLB slave model during secondary read requests. When programmed to
recognize PLB_SAValid, the PLB slave model asserts addrAck during PLB_SAValid and queues
secondary read requests which are processed after primary requests are complete. The
PLB_rdPrim and PLB wrPrim signals are used to switch secondary requests to primary status
within the model. When this parameter is used in the configuration statement of the slave, the
read_addr_pipeline_mode will be constant for the entire simulation session.
• * write_addr_pipeline_disable = [1 bit] 0=SAValid recognized,1=SAValid ignored default:0
This parameter specifies whether the PLB core secondary address valid control signal is
recognized by the PLB slave model during secondary write requests. When programmed to
recognize PLB_SAValid, the PLB slave model asserts addrAck during PLB_SAValid and queues
secondary write requests which are processed after primary requests are complete. The
PLB_rdPrim and PLB wrPrim signals are used to switch secondary requests to primary status
within the model. When this parameter is used in the configuration statement of the slave, the
write_addr_pipeline_mode will be constant for the entire simulation session.
• * data_pipeline_mode = [1 bit] 0=overlapped DAck mode,1=sequential DAck mode default:0
This parameter specifies whether the PLB slave model may assert read and write data
acknowledge signals simultaneously. When programmed for sequential DAck mode, the slave
model will not assert read and write DAcks in the same clock. When this parameter is used in the
configuration statement of the slave, the data_pipeline_mode will be constant for the entire
simulation session.
• * msg_disable = [bit] 0=disabled 1=enabled default:0
This parameter disables all message generation of the PLB slave model, including data error
message generation.
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