Processor Local Bus Functional Model Toolkit User's Manual

This parameter specifies the mode in which lock is deasserted. This may be specified as clock
mode or cycle mode. Clock mode specifies the deassertion of lock as the number of clocks from
when lock was previously asserted. Cycle mode specifies the number of cycles to expire before
lock is deasserted. In cycle mode, lock is deasserted when Mn_request is deasserted during the
last locked cycle.
• * unlock_delay = [integer:range 1 to 255]
This parameter specifies the number of clocks to deassert lock after it was previously
asserted, or the number of cycles to elapse before it is deasserted. The mode for the
deassertion of lock is specified with the unlock_mode parameter. A cycle is defined by the
assertion of PLB_MAddrAck, PLB_MTimeout or M_abort. Note that if two commands are
given, both with an unlock_delay > 1, the unlock_delay from the first command will be used to
deassert M_buslock and not the second. For example:
write(addr=08f9f360,size=0001,priority=11,lock=1,unlock_delay=4,unlock_mode=cycle)
read(addr=08f9f460,size=0001,priority=11,lock=1,unlock_delay=3,unlock_mode=cycle)
In this case, the M_buslock will be deasserted 4 cycles after the write request. The
unlock_delay of 3 will be ignored.
• * type = [3 bit] default:000
This parameter specifies the Mn_type signals of the PLB. The valid size combinations are listed in
the PLB architecture specifications under transfer qualifier signals. The default value is a memory
transfer.
• * compress = [1 bit] default:0
This parameter enables the assertion of the Mn_Compress signal for the duration of the master
request phase.
• * guarded = [1 bit] default:0
This parameter enables the assertion of the Mn_Guarded signal for the duration of the master
request phase.
• * ordered = [1 bit] default:0
This parameter enables the assertion of the Mn_Ordered signal for the duration of the master
request phase.
• * lockErr = [1 bit] default:0
This parameter enables the assertion of the Mn_lockErr signal or the duration of the master
request phase.
• burst_count = [integer]
This parameter specifies the total number of data transfers when a burst cycle is used with the size
parameter. The master will continue to execute cycles until an internal transfer counter equals the
burst_count parameter. Note that this parameter is only used when a burst cycle is specified with
the size parameter. For a burst of one data transfer, the rd/wr_burst signals will not be asserted,
and the burst_count parameter should be set to ‘1’ or simply omitted from the command.
Note: For fixed length bursts, the PLB Architecture allows the pre-mature de-assertion of the
M_rd/wrburst signal before the number of data beat transfers specified by the byte enables.
The PLB Architecture also allows Masters to continue bursting beyond the fixed length burst
beat count if a slave burst terminate signal is NOT received during a fixed length burst transfer.
36 Processor Local Bus Functional Model Toolkit Version 4.9.2