Processor Local Bus Functional Model Toolkit User's Manual

This parameter specifies the data which will be used to update the PLB master internal memory.
An immediate 4-byte data value or an internal register may be used.
Example: mem_update(addr=00001000,data=05060708)
6.3.6 Reg_Update () Command
The reg_update command updates an internal master register during the decode and execution of
master bus commands. Each reg_update command executes in one PLB clock cycle.
• DST = [4 byte]
This parameter specifies the 32-bit destination register of the internal register to be updated.
Example: reg_update(R0=05060708)
6.3.7 Send () Command
The send command causes a vectored intercommunication signal to be asserted at the
corresponding level parameter and does not directly cause PLB bus activity. The synch_Out signal is
asserted for one clock per send instruction and may be used to communicate between multiple model
instantiations in order to coordinate bus activity. The send is executed sequentially along with the
read/write commands and is a serializing instruction, meaning that the model waits for all previously
issued bus cycles to complete on the bus before sending its intercommunication signal.
• level = [integer: range 0 to 31]
The level parameter allows for one or more send signals to be asserted on the synch_Out bus.
Multiple levels may be used in the same clock by listing more than one level. Note that it is possible
for a user to use the same intercommunication level with multiple masters, however the assertion
of the same level in the same clock by multiple masters will not be distinguished on the
intercommunication send vector.
• * req_delay = [integer]
This parameter specifies how many clock cycles the PLB master needs to wait before it asserts the
synch signal for the corresponding send instruction. The counter starts when all cycles on the bus
are complete since the send instruction is a serializing instruction.
Example: send(level=1)
6.3.8 Wait () Command
The wait command causes the bus master to suspend instruction decode until an intercommunication
signal is received. The wait instruction is a serializing instruction and is executed sequentially along
with the read/write commands. In addition, all previously issued bus cycles need to complete on the
bus before the intercommunication signal on the synch_In bus is recognized.
• level = [integer: range 0 to 31]
The level parameter specifies the synch_In signal to be sampled before instruction execution
continues.
Example: wait(level=1)
38 Processor Local Bus Functional Model Toolkit Version 4.9.2