Processor Local Bus Functional Model Toolkit User's Manual

This parameter specifies the seed to be used for the auto data feature of the model. The slave
model forms a seed using this root_seed and the byte address. The user may change the initial
seed to change the random number sequences which are generated, which in turn will produce
varying slave data.
6.4.2 Mem_Init () Command
The mem_init command initializes slave memory at simulation time 0.
• addr = [4 byte]
This parameter specifies the 32-bit address.
• data = [4 byte]
This parameter specifies the slave memory data to initialize in the corresponding PLB device.
6.4.3 Read_Response (), Write_Response () Commands
These commands specify attributes for a slave cycle read or write response when an address decode
is true. Read_response commands are used to initialize the PLB slave response.
• * aack_delay = [integer] default=0
This parameter specifies the number of clocks to wait before asserting Sl_addrAck from the time
PLB_PAValid or PLB_SAValid is active. For example, an aack_delay value of 0 will assert
Sl_addrAck together with PLB_PAValid and an aack_delay of 1 will assert Sl_addrAck one clock
after PLB_PAValid is recognized.
• * rearb_delay = [integer] default=0
This parameter specifies the number of clocks to wait before asserting the Sl_rearbitrate signal
from the clock that PLB_PAValid was previously asserted. No Sl_addrAck is asserted if the
rearb_delay parameter is used. Note that rearb_delay is not a valid configuration.
• * dack_delay = [integer] default=0
This parameter specifies the number of clocks to wait before asserting the first data acknowledge
control signal for a read_response or write_response. This parameter is relative to the earliest legal
assertion of Sl_rdDAck and Sl_wrDAck. For example, a DAck_delay value of 0 for a
read_response causes the Sl_rdDAck signal to be asserted 2 clocks after Sl_addrAck is asserted,
which is the earliest legal PLB slave data response time for the first Sl_rdDAck. A DAck_delay
value of 0 for a write_response causes the Sl_wrDAck signal to be asserted together with the
Sl_addrAck assertion, which is the earliest legal PLB slave data response time for the first
Sl_wrDAck.
For line and burst transfers, the dack_delay parameter can be used to specify delays between
dacks for a multiple data beat transfer. This is accomplished with the following syntax:
read_response(dack_delay=2*) or configure(dack_delay=2*)
These bfl statements will produce a delay of 2 between dacks for a line or burst transfer.
Another available option is to specify different delays between dacks for a multiple data beat
transfer. This is accomplished with the following syntax:
read_response(dack_delay=2-3-4-5)
46 Processor Local Bus Functional Model Toolkit Version 4.9.2