Processor Local Bus Functional Model Toolkit User's Manual

This mode enables the user to generate PLB read/write bus transactions and perform other
operations using commands which are decoded and executed from within the PLB master model.
These commands are parsed by the BFC, loaded into the PLB master model at simulation time 0,
and decoded from an internal command array after PLB reset is de-asserted. The following is an
example of how to specify a 32-bit single read transaction:
read(addr=00001000,size=0000,be=1111)
Command mode is the default mode for the master model, and the user is not required to specify a
BFL configuration parameter for this mode.
• Auto Mode
This mode enables PLB read/write bus cycles to be generated automatically without the need for
read/write master commands in the bfl. In this mode, the PLB master model will generate PLB
cycles automatically based on an internal random number generator and pre-programmed
minimum and maximum delays of the available parameters. The random number generator selects
a new delay value between the minimum and maximum using a uniform distribution function. The
minimum and maximum range may be initialized by the user through a configuration command.
The PLB master model will use auto mode when a configuration command enables it, such as:
configure(master_auto_mode=true)
5.2.5 Burst Operations
The PLB master model supports the PLB burst protocol. The model accesses the internal master
memory during the initial bus request and also during each data phases of the burst transfer. The PLB
master model terminates a burst transfer when the user specified number of data transfers has
occurred or when a slave terminates the burst transfer with a burst terminate signal. The PLB master
model supports a burst_continue_mode where the PLB master will request the bus again if a slave
terminate signal is received and the PLB master has more data to transfer. To configure the PLB
master model for burst_continue_mode, use the following configuration statement:
configure(burst_continue_mode=true)
The PLB master model also supports the PLB fixed length burst protocol. The master model will
automatically de-assert the M_rd/wrBurst signal when: the ‘BE’ parameter is non-zero; the ‘size’
parameter indicates a burst cycle; the corresponding number of data transfers takes place.
Note: For fixed length bursts, the PLB architecture allows the pre-mature de-assertion of the
M_rd/wrburst signal before the number of data beat transfers specified by the byte enables.
The PLB architecture also allows masters to continue bursting beyond the fixed length burst
beat count if a slave burst terminate signal is NOT received during a fixed length burst transfer.
To allow verification of this architectural flexibility, the BURST_COUNT parameter can be
programmed to a different number of beats than that specified on the byte enables. When the
BURST_COUNT parameter is less than the BE data beat count, the burst signal will be prematurely
de-asserted. When the BURST_COUNT is greater than the BE data beat count, the
master will continue bursting IF a slave burst terminate signal was not asserted to the master.
IT IS STRONGLY RECOMMENDED THAT LOGIC DESIGNS WHICH SUPPORT BURST
AND FIXED LENGTH BURST BE TESTED THOROUGHLY WITH ALL COMBINATIONS OF
BYTE ENABLES, MASTER BURST ABORTS, AND SLAVE BURST TERMINATES TO
MAXIMIZE CORE COMPATIBILITY AND COMPLIANCE.
Version 4.9.2 PLB Bus Models 19