Processor Local Bus Functional Model Toolkit User's Manual

This response mode allows the user to change the slave read/write response on a test case basis.
For each PLB master cycle that is received, the PLB slave model uses an internal configuration
register to respond to all PLB read or write memory cycles which are active within its address
space. This mode is the default configuration of the PLB slave model. The configuration delay
values can be initialized using configuration commands such as:
configure(read_aack_delay=2,read_dack_delay=2-1-1-
1,write_aack_delay=1,write_dack_delay=1-1-1-1)
This mode is the default mode of the PLB Slave model, and the user is not required to specify a
BFL configuration parameter for this mode.
• Command Mode
This response mode enables the user to change the slave read/write response on a transaction
basis. For each PLB master cycle that is received, the PLB slave model uses a response
command from an internal read or write command array when a PLB read or write memory cycle is
active within its address space. The PLB slave model uses command mode instead of
configuration mode when read/write response commands are programmed in a test case such as:
read_response(aack_delay=2,dack_delay=3)
When the BFC parses “response” commands, it automatically initializes the appropriate internal
slave model register to enable “command” mode. The user is not required to specify a BFL
configuration parameter to use this mode.
• Auto Mode
This response mode enables various cycle responses without using pre-programmed read/write
slave response commands. In this mode, the PLB slave model generates address and data phase
completion signals automatically, based on an internal random number generator and preprogrammed
minimum and maximum delays. The random number generator selects a new delay
value between the minimum and maximum using a uniform distribution function. The minimum and
maximum range may be initialized by the user using a configuration command. The PLB slave
model requires a configuration command for enabling auto mode. The following configure
statement is an example:
configure(slave_auto_mode=true)
5.3.4 Internal Slave Data Memory Structure and Look-Up Algorithms
The PLB slave model contains an internal memory array which can be initialized by the user with
mem_init bus functional commands. Each entry of the memory array represents a 64-bit address and
128-bit data.
– PLB_slave_addr_array(0 to 63) - bits 0 to 61:address, bit 62:dirty bit, bit 63:valid bit
– PLB_slave_data_array(0 to 127) - 4 word data field
– PLB_slave_dirty_array(0 to 15) - bytes written (half word) field
Bits 62 and 63of the PLB_slave_addr_array are not used for addressing bytes within the PLB slave
model memory, but they are used by the internal slave model memory interface logic to maintain the
status of memory array elements. The valid bit is set during model initialization for each memory entry
used and also during simulation when a memory entry is allocated in the case of a write memory
access miss. When a write command reloads a memory entry with bus data, the dirty bit is set. This
24 Processor Local Bus Functional Model Toolkit Version 4.9.2