Processor Local Bus Functional Model Toolkit User's Manual

may be used with test environments to check that bus commands are executed and master memory
is updated in addition to data miscompares.
For each byte that is written to the slave memory array during simulation of PLB write cycles to the
slave, the PLB_slave_dirty_array is updated to indicate that the corresponding byte has been
updated. This feature can be used in simulation environments which need to detect or count exactly
which bytes were written to in the slave so that a more comprehensive checking algorithm may be
implemented. In addition, there are two integer variables within the slave memory process which
accumulate the total number of bytes which have been read from the slave memory array and also
the total number of bytes which have been written to the array. These two variables are called:
– slave_mem/total_bytes_written
– slave_mem/total_bytes_read
The default size of the slave memory array is 64k bytes. This may be increased or decreased by
updating the PLB_slave_mem_array_size parameter in the PLB_DCL declaration HDL file of the
toolkit.
The PLB slave model supports two different memory look-up algorithms used to access the internal
memory arrays: fully associative and direct mapped. Each of these is described below:
• Fully associative, linear search look-up mode
The default mode for the PLB slave model is linear search mode. This algorithm provides the
flexibility to initialize the slave model with many non-contiguous data patterns within an entire 64-bit
address range. In the linear look-up mode, each array element status is maintained by the slave.
Initialization with mem_init commands causes the valid bit to be set. Any bus cycles which have an
address that matches a valid entry in the memory array will use the memory array for the bus
functional command operation. For write cycles, the internal master data memory will be updated
when Sl_wrDAck is asserted. For read cycles, data from the internal slave memory is loaded into a
buffer one clock before Sl_rdDAck assertion.
• Direct mapped mode
When the PLB slave model is programmed in direct mapped mode, a subfield of the address
(PLB_Abus) is used to directly reference the PLB slave internal memory. The direct mapped mode is
useful when simulations contain many contiguous slave address, as the lookup algorithm is more
efficient than the linear search mode.
Note: The internal slave address subfield is automatically calculated by the model as the slave
memory configuration parameters are set in the plb_dcl.vhd file. The user is not required to
configure these indices within the toolkit.
5.3.5 Ordered Write Cycles (PLB_ordered)
When the slave model acknowledges a write cycle when PLB_TAttribute[8] signal is active, the PLB
slave model will delay all subsequent internal data accesses until the previous write cycle is internally
complete. The PLB slave model, however, may acknowledge additional cycles (assert Sl_addrAck)
during ordered writes.
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