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Processor Local Bus Functional Model Toolkit User's Manual

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Chapter 8. PLB Compliance Checks<br />

8.1 Monitor <strong>Model</strong><br />

The PLB monitor model attaches to the PLB bus and generates informational architectural<br />

compliance messages during simulation. The model is passive in that it does not participate in any<br />

bus protocol signal assertions, but it samples PLB signals in every clock to keep track of the state of<br />

the PLB bus and inform the user of any detectable PLB compliance problems. Messages are<br />

generated to the simulator console, which also may be re-directed to file systems in most simulation<br />

environments.<br />

8.2 Terminology<br />

The following terminology is used in the specification of the PLB monitor compliance checks:<br />

• Active: refers to the situation when a signal is at its true state (a logical 1).<br />

• Asserted: refers to the situation when a signal transitions from inactive to its active state.<br />

• Inactive: refers to the situation when a signal is at its false state. (a logical 0)<br />

• Deasserted: refers to the situation when a signal transitions from active to its inactive state.<br />

• Time-out: refers to the event which occurs when there have been 16 cycles of non-response from a<br />

slave (or Mn_abort) since the assertion of PLB_PAValid. The 16 cycle count may be interrupted by<br />

the slave response of Sln_wait active. And the count will remain interrupted for as long as the wait<br />

is active. The count will be terminated by slave asserting Sln_rearbitrate or Sn_addrAck. The count<br />

may also be terminated by the master asserting Mn_abort (given no Sn_addrAck has been<br />

received). If the count reaches 16 and none of the terminating responses (from master or slave)<br />

have been asserted then a time-out has occurred.<br />

8.3 Address Map Set-up Error<br />

An error message is issued when PLB_reset is de-asserted and the PLB monitor slave address map<br />

has not been initialized.<br />

8.4 Slave Interface/PLB Core OR Logic Error<br />

An error message is issued when the OR’ed value of all the PLB slave control outputs does not equal<br />

the output of the system OR gates which are inputs to the PLB arbiter.<br />

Version 4.9.2 PLB Compliance Checks 69

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