Processor Local Bus Functional Model Toolkit User's Manual

3.2 Instantiating PLB Slave Designs Under Test
When instantiating a PLB slave design under test, connect the PLB signals in the test bench to the
new device and remove a PLB slave model instantiation. Ensure that the PLB slave address map has
non-overlapping slave address space. The PLB slave model instantiation generics/parameters have
a default slave address mapping as follows:
Device 0 00000000-0003FFFF
Device 1 00040000-0007FFFF
Device 2 00080000-000BFFFF
Device 3 000C0000-000FFFFF
The PLB slave model has parameters for the address decode in the HDL file. These may be updated
by the user to re-program the default slave address space for a single PLB slave instantiation. When
multiple slave models are connected to a single PLB core, the user must ensure that the slave
decode maps are mutually exclusive within a test bench. This can be accomplished through the BFL
configure command, generic statements in the VHDL instantiations, or Verilog parameters in the
model HDL files.
3.3 Instantiating PLB Master Designs Under Test
When instantiating a PLB master design under test, connect the master to the PLB master interface
of the PLB core/arbiter. Each master will have an independent PLB interface as defined in the PLB
architecture specification.
Each toolkit model uses intercommunication signals called Synch_in(0 to 31) and Synch_out(0 to 31)
to synchronize events in the test environment. The Synch_in(0 to 31) is the logical OR of all the
Synch_out outputs of each instantiated models in the simulation environment which uses the
intercommunication bus. When instantiating toolkit models which need to support the send/wait
commands as described in “PLB Bus Functional Language” on page 29, ensure that the
intercommunication logic within the test bench is updated to reflect the additional model
instantiations.
3.4 VHDL Signal Types
The signal interface for the VHDL bus functional model wrappers and test bench are declared as
IEEE std_logic and std_logic_vector signal types. If the bus functional models are integrated with a
test bench environment which uses bit and bit_vector types, the wrappers may be eliminated so that
type conversions do not have to be included in the model interfaces. When the wrappers are not
used, please note that the I/O for each PLB toolkit model component contains primary inputs for
configuration signals rather than the VHDL generic declarations which are in each wrapper.
3.5 IEEE Packages
The VHDL version of the PLB core RTL is translated from Verilog to VHDL with a source level
language translator. The translated VHDL calls out some IEEE packages such as:
10 Processor Local Bus Functional Model Toolkit Version 4.9.2