Processor Local Bus Functional Model Toolkit User's Manual

An error message is issued when a master changes this transfer qualifier from when a request to
transfer is made until the addressed slave asserts its Sln_addrAck, or the transfer is terminated via
Mn_abort, PLB_MnRearbitrate, or Mn_Timeout.
8.6.10 Mn_ABus/Mn_UABus
The following error messages are issued for this signal:
• Error 1.12.1
An error message is issued when a master changes these transfer qualifiers from when a request
to transfer is made until the addressed slave asserts its Sln_addrAck, or the transfer is terminated
via Mn_abort, PLB_MnRearbitrate, or Mn_Timeout.
• Error 1.12.2
An error message is issued when the Mn_Abus word address is non-zero during a line write
transfer.
• Error 1.12.3
An error message is issued:
– when the master has a non-aligned half word burst address for half word burst transfers.
– when the master has a non-aligned word burst address for word burst transfers.
– when the master has a non-aligned double word burst address for double word burst transfers.
– when the master has a non-aligned quad word burst address for quad word burst transfers.
• Note1.12.4
An note message is issued when the Mn_Abus word address is non-zero during a line write
transfer.
8.6.11 Mn_abort
The following error messages are issued for this signal:
• Error 1.13.1
A warning message is issued if Mn_abort is asserted without a Mn_Request.
8.6.12 Mn_wrDBus(0: PLB DATA BUS WIDTH)
The following error messages are issued for this signal:
• Error 1.14.1
An error message is issued when a master changes this transfer qualifier from when a write
request to transfer is made until the addressed slave asserts its Sln_addrAck, or the transfer is
terminated via Mn_abort, PLB_MnRearbitrate, or Mn_Timeout.
• Error 1.14.2
76 Processor Local Bus Functional Model Toolkit Version 4.9.2