Processor Local Bus Functional Model Toolkit User's Manual

6.3.3 Reg_Init () Command
The reg_init command initializes an internal master register and is only executed at simulation time 0.
• DST = [4 byte]
This parameter specifies the master 32-bit register to initialize. DST may be CR, SR, or R0-31
Example: reg_init(R0=01020304)
6.3.4 Read () and Write () Bus Cycle Commands
The read/write bus cycle commands initiate read or write cycles on the PLB bus by causing the bus
master to assert the M_request signal. These commands are executed sequentially, therefore the
completion of the cycles on the PLB bus influence the simulation time at which the commands are
decoded. The following is a list of possible read/write parameters:
• addr = [4/8 byte]
This parameter specifies the 32-bit or 64-bit address.
• tattr/tattribute= [4 hex] default:0000
This parameter enables and specifies the tattribute value.
Example: read(req_delay=3,addr=00001000,size=0000,be=1111,tattr=A001)
• * be = [4/8/16 bit]
This parameter specifies the Mn_BE (byte-enable) signals of the PLB. The valid byte-enable
combinations are listed in the PLB architecture specifications under transfer qualifier signals. This
parameter is required for all nonburst and non-line transfers.
• size = [4 bit]
This parameter specifies the Mn_size signals of the PLB. The valid size combinations are listed in
the PLB architecture specifications under transfer qualifier signals.
• * msize = [2 bit]
This parameter specifies the Mn_MSize signals of the PLB. The valid size combinations are listed
in the PLB architecture specifications under transfer qualifier signals. Note that this parameter will
be ignored if MSize was previously defined as a configuration parameter.
• * req_delay = [integer]
This parameter specifies the number of clock cycles for the master to wait before it asserts its
M_request signal for the corresponding read or write cycle.
• * lock = [1 bit] default:0
This parameter specifies whether to assert Mn_busLock with Mn_request. If the parameter is not
specified then lock is not asserted. The PLB will be locked when a valid PLB_MnaddrAck is
asserted. When using the lock parameter, an unlock parameter is required in the same instruction.
The lock signal is automatically deasserted if a rearbitrate occurs.
• * unlock_mode = [enumerated type] default:cycle
Version 4.9.2 PLB Bus Functional Language 35