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Processor Local Bus Functional Model Toolkit User's Manual

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6.3.11 Compare () Command<br />

The compare command enables the user to compare two values and store the results in the condition<br />

register. Each compare instruction executes in one PLB clock cycle.<br />

• SRC (two are required)<br />

This parameter specifies the internal register value to be used as a source of the compare<br />

instruction. Each compare instruction requires two SRC parameters. Valid values are SR,R0-31.<br />

• DST<br />

This parameter specifies the condition register destination of the compare instruction. Valid values<br />

are CR0-7.<br />

Example: compare(R0,R1,CR1)<br />

6.3.12 Add () Command<br />

The add command updates an internal master register with the result of an addition between an<br />

internal register and an immediate value. Each add command executes in one PLB clock cycle.<br />

• DST, [hex value up to 4 bytes]<br />

These two parameters specify the 32-bit internal destination register to be updated and the<br />

immediate hexadecimal value to be added to the destination register. The DST must be R0-31, SR,<br />

or CR.<br />

Example: add(R0,01)<br />

6.3.13 Sub () Command<br />

The sub command updates an internal master register with the result of a subtraction between an<br />

internal register and an immediate value. Each sub command executes in one PLB clock cycle.<br />

• DST, [hex value up to 4 bytes]<br />

These two parameters specify the 32-bit internal destination register to be updated and the<br />

immediate hexadecimal value to be subtracted from the destination register. The DST must be R0-<br />

31, SR, or CR.<br />

Example: sub(R0,01)<br />

6.3.14 AND () Command<br />

The AND command updates an internal master register with the result of a bit-wise AND operation<br />

between an internal register and an immediate value. Each AND command executes in one PLB<br />

clock cycle.<br />

• DST, [hex value up to 4 bytes]<br />

These two parameters specify the 32-bit internal destination register to be updated and the<br />

immediate hexadecimal value to be AND'd with the destination register. The DST must be R0- 31,<br />

SR, or CR.<br />

Example: and(R0,FFFFFFF0)<br />

40 <strong>Processor</strong> <strong>Local</strong> <strong>Bus</strong> <strong>Functional</strong> <strong>Model</strong> <strong>Toolkit</strong> Version 4.9.2

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