Processor Local Bus Functional Model Toolkit User's Manual

5.3.1 Slave Model Operation
The PLB slave model operation section discusses the slave bus commands and modes, internal
slave data memory structure and look-up algorithms, ordered write cycles (PLB_ordered), internal
slave memory checking, burst modes, conversion cycles with different PLB device sizes, and pipeline
modes.
5.3.2 Slave Bus Commands and Modes
The PLB slave model responds to PLB memory cycles (PLB_type=000) when there is a valid request
on the PLB bus and the PLB address is within the PLB slave’s configured address space. Separate
read_response and write_response commands allow programmable, overlapped read and write data
phases. The slave model stores the read and write response parameters in separate command
arrays which allows independent and parallel control of the data buses. Although address phases
occur sequentially, it is possible for a slave to perform out of order memory access relative to the
address phases depending on how the master cycles are generated and how the slave model is
programmed to respond to the bus cycles. The PLB slave model memory uses the Sl_rdDAck and
Sl_wrDAck signals to perform internal memory accesses needed to satisfy PLB read and write bus
cycle requests.
In the PLB slave model, memory access for reads always occurs one clock before the Sl_rdDAck
assertion, and the memory access for writes always occurs in the clock that Sl_wrDAck is asserted.
Also, writes have precedence in the memory access logic of the PLB slave memory model. If
Sl_rdDAck is asserted in a cycle after a wrDAck, then the read data always reflects the new data
written. If a rdDAck is asserted in a cycle before or during a wrDAck, then the read data always
reflects the old data. Since the PLB architecture allows out of order rd/wrDAcks with respect to
addrAck from the same slave, it is the responsibility of the system designer to resolve data coherency
issues when simultaneous write/read cycles occur.
Slave memory and configuration parameters are initialized at simulation time 0 with the command file
generated by the PLB bus functional compiler. The slave response commands are initialized in the
slave command array at simulation time 0, but they are executed sequentially during simulation.
Separate read and write internal command pointers advance when bus transfers complete, a
rearbitrate occurs, or a master abort occurs. Intermediate data checking during simulation can be
done by using memory check commands which are executed when an intercommunication signal is
received by the slave. These memory check commands are independent of the slave response
command flow.
The default size of the bus command array is 256 entries. This may be increased or decreased by
updating the PLB_slave_CMD_array_size parameter in the PLB_DCL declaration HDL file of the
toolkit.
5.3.3 Command Modes
This section discusses the possible modes that are available for a PLB slave device. PLB slaves may
be configured to act in either Configuration mode, Command mode, or Auto mode. A description of
these modes are:
• Configuration Mode
Version 4.9.2 PLB Bus Models 23