Processor Local Bus Functional Model Toolkit User's Manual

When the decode unit issues a bus request, it continues decoding and executing additional
instructions from the command memory as long as it is not waiting on an external event. An example
of an external event would be a synchronization signal. In addition, a request delay parameter may
suspend the decode unit issuance of commands to the bus unit until an internal command delay
counter has expired.
The default size of the bus command array is 1024 entries. This may be increased or decreased by
updating the PLB_Master_CMD_Array_Size constant in the declarations HDL file of the toolkit.
5.2.3 Internal Master Data Memory
The PLB master model contains an internal memory array which can be initialized by the user with
mem_init bus functional commands. Each entry of the memory array is maintained by the master
model during simulation. During this initialization with mem_init commands, a valid bit is set for each
address entry. Any bus functional commands which specify an address that matches a valid entry in
the memory array will use the memory array for the bus functional command operation. The data
used in mem_init statements provides the expect data that is used for the read data comparison
checks within the master model. It also provides the data used during a write transfer to a memory
address.
For write cycles, the internal master data memory will be used as source data when the bus functional
command address matches the command array. For read cycles, the data which is received from the
PLB bus will automatically be compared with the internal master data memory.
Error messages will be generated when data miscompares occur. Only the valid bytes for a particular
command will be checked. The valid bytes are determined by the transfer size as defined in the PLB
architecture.
The memory array is declared as a linear array of 64-bit address/control and 128-bit data for each
array entry:
– PLB_Master_Addr_Array(0 to 63) - bits 0 to 61:address field, bit 62:dirty bit, bit 63:valid bit
– PLB_Master_Data_Array(0 to 127) - 4 word data field
The valid bit is set during model initialization for each memory entry used and when a memory entry is
allocated in the case of a read memory access miss. When a read command reloads a memory entry
with bus data, the dirty bit is set. This may be used with test environments to check if bus commands
have executed and caused a master memory update in addition to data miscompares.
The default size of the master memory array is 64k bytes. This may be increased or decreased by
updating the PLB_Master_Mem_Size in the declaration HDL file of the toolkit.
5.2.4 Command Modes
This section discusses the possible modes that are available for a PLB master device. PLB masters
may be configured to act in either Command mode or Auto mode. A description of these modes are:
• Command Mode
18 Processor Local Bus Functional Model Toolkit Version 4.9.2