Processor Local Bus Functional Model Toolkit User's Manual

1.3 PLB Implementation
The PLB implementation consists of a PLB core to which all masters and slaves are attached. The
logic within the PLB core consists of a central bus arbiter and the necessary bus control and gating
logic.
The PLB architecture supports up to sixteen master devices. However, PLB core implementations
supporting less than sixteen masters are allowed. The PLB architecture also supports any number of
slave devices. However, it should be noted that the number of masters and slaves attached to a PLB
core in a particular system will directly affect the performance of the PLB core in that system.
Figure 2 shows an example of the PLB connections for a system with three masters and three slaves.
Arbitration
Address
& Transfer
Qualifiers
Write
Data
Bus
Control PLB
PLB
Master 1
PLB
Masters
Central Bus Arbiter
Bus
Control
& Gating
Logic
Read
Data
Bus
Status &
Control
PLB
Core
Address
& Transfer
Qualifiers
Write
Data
Bus
Control
4 Processor Local Bus Functional Model Toolkit Version 4.9.2
Shared Bus
OR
OR
Figure 2. Physical Implementation of the PLB
PLB
Slaves
Read
Data Bus
Bus
Status &
Status Control &
Control