Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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Wouldn’t it be nice to have complex cores already created and optimized for Xilinx FPGAs? You will use the Xilinx Architecture Wizard to optimize cores for instantiation. You will learn to: • Use Xilinx ISE Project Navigator to implement an FPGA design • Read suitable reports to determine whether design goals were met • Assign pin locations with PACE to enhance performance • Configure a clocking scheme with the Architecture Wizard software • Use the Constraints Editor to create global timing constraints, which drive performance • Specify software options that can boost performance • Use synchronous design techniques to create reliable designs and improve performance The Fundamentals of FPGA Design course provides the necessary foundation to begin using Xilinx FPGAs, create reliable designs, improve area, and increase performance. The prerequisites for this course are basic logic/digital design knowledge and basic VHDL or Verilog knowledge. Designing for Performance Course Are you having trouble meeting your performance goals? Do you find that changing software options doesn’t help – or makes matters worse? In the Designing for Performance course, we will teach you a simple timing closure flow (see Figure 1), as well as which options to use and what to expect. For example, say that you need to increase your performance by 25%. What should you do? Using the techniques taught in this course, you can take a design that can barely achieve 125 MHz performance and by the end of the course increase performance to 200 MHz – an increase of 38%. Are you having trouble synchronizing an incoming signal? Do you need to cross data from one clock domain to another? In 1 2 3 4 5 6 Done Use Proper Coding Techniques Drive Your Synthesis Tool Apply Global Xilinx Constraints Implement Increase Place & Route Effort Level Done 6c No 7 Apply Multi-Cycle and False Path Constraints 8 9 10 11 Done Specify Pin Constraints 106 Xcell Journal Third Quarter 2005 4a Yes 6a Yes Yes Meets Timing? No Reasonable Performance Objectives Implement Meets Timing? Implement Meets Timing? No No 6b No 7b No Review Critical Paths in the Code Rewrite code to improve speed Apply Critical Path Constraints in Synthesis Done Implement Meets Timing? Implement with MAP-Timing Options or Run Multi-Pass Place & Route Done Done 7a 9a Yes Finish Routing Placements 10a Yes 4b 7c 9c 10b No Meets Timing? No Floorplan Implement 11a Yes Meets Timing? 11b 11d 11c No 9b No No Start Over/Rewrite Code Figure 1 – Timing closure flow chart No Increase Place & Route Effort Level All Multi-Cycle and False Paths Not Identified All Critical Paths Not Identified Floorplan Hindered Timing Floorplan Helped But Did Not Meet Timing
BIDIR_PAD(7.0) BIDIR this course, we will further explore synchronous design techniques, teaching you how to pipeline, duplicate high-load signals, and use synchronization circuits. Do you find that your synthesis software settings do not always accomplish what you would like? Are you not certain what each option does? Utilizing synthesis settings, you can increase the lab design’s performance by as much as 20%. Does your design have multi-cycle and false paths? By correctly constraining the lab design with multi-cycle and false path constraints (see Figure 2), you will find that Translate Map Place & Route Control Registers Floorplanned UCF Guide File Previously Map NCD Guide File Previously PAR NCD Incremental Implementation 6 Reimplement using guide files. - As a guide, apply the previous map.ncd and par.ncd files - All blocks without modification will maintain previous placement and routing - Once all of the unchanged logic is placed and routed, the new logic will be placed and routed Top Level A B C Incremental Synthesis Make your changes incrementally; one module at a time. B1 B2 C1 C1 - Resynthesize only the block that has changed 5 the design runs 20% faster than originally noted. Correctly constrained, your design may benefit by even greater amounts. How do you find failing timing constraints – and how do you fix them? Understanding how to use the information provided by Xilinx Timing Analyzer is the central catalyst to increase the course’s lab design performance by 38%. How do you use the myriad of implementation settings to improve results? Do you need to increase your performance by 2%, 10%, or more? You will identify which advanced implementation options provide A B C Status Registers Control_Enable Status_Enable BIDIR_BUS(7:0) False Paths Figure 2 – False paths through bi-directional pad the most benefit for each situation. You will learn to: • Write HDL code to efficiently target Virtex-II-based device resources • Create customized and optimized cores in CORE Generator software • Use Timing Analyzer to pinpoint timing errors and identify a strategy to improve performance • Use design/coding techniques and software options to achieve timing closure • Correctly and completely constrain your design with global and path-specific timing constraints in the Xilinx Constraints Editor • Improve design performance and manage software runtime by using the optimal software settings The knowledge obtained from the first two courses in this track will provide you with the necessary knowledge to tackle Third Quarter 2005 Xcell Journal 107 Top Level 1 A B C B 1 B 2 C 1 Figure 3 – Incremental design techniques/design flow Create Incremental Blocks Partition boundaries to match the blocks that you would like to preserve. Do not allow the synthesis tool to optimize across these boundaries. - Individual netlists for each incremental block - Create two to eight blocks, and each block will require floorplanning 2 Synthesize 4 A B Implement A B C C 3 Synthesize each block. - Write out individual netlist for each block - For block netlists, disable I/O insertion - Apply: do not insert clock buffer Floorplan AREA Constraints Use Floorplanner (or PACE) to layout area constraints for each of the preserved blocks. - Use non-overlapping constraints Implement the design until timing objectives are met. - Use floorplan information in the UCF - May require several implementation iterations with a high level - Use incremental design techniques to maintain these good results
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Xcell Issue 54 Third Quarter 2005 j
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EDITOR IN CHIEF Carlis Collins edit
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THIRD QUARTER 2005, ISSUE 54 Xcell
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Hardware Said ... The design flow s
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The second idea is to have the hard
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and automatic module generation wil
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Designing Control Circuits for High
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Figure 2 - Implementing an FSM in S
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Let’s consider these challenges i
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demonstrated by Dr. Howard Johnson,
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Virtex-4 beats competing FPGAs in e
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Using Precision Sythesis, Block Mul
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14-Bit, 125Msps ADC Only 395mW Lowe
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Non-Symmetric Aspect Ratios/FWFT Ap
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QWERTY Building Blocks Our solution
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FPGA-Based Video Games Implementing
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The Atari 2600 Video Computer Syste
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The architecture wizards inside ISE
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Smart Telematics Systems from Xilin
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interfaces available, Microsoft int
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POWER MANAGEMENT Design Techniques
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Power Estimation Tools Xilinx provi
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POWER MANAGEMENT Performance vs. Po
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POWER MANAGEMENT is the first time
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Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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