Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

Bus Triggering and Display
Traditional oscilloscopes provide digital
triggering capabilities that allow them to
trigger on patterns across analog channels.
With a four-channel oscilloscope, you can
trigger on a single pattern that is as wide as
four signals.
Debug often requires looking at buses
using a specific event as the trigger condition.
Using an MSO’s digital channels, you
can trigger on a digital pattern as wide as
16 signals. This can be a powerful capability
if you need to look at a state machine,
an embedded microcontroller, or a data
bus. In addition, you can also trigger
and capture measurements
across all four analog channels,
extending the trigger width up to
20 signals, as shown in Figure 1.
Correlating Analog and
Digital Measurements
Although you can use the digital
channels to make strictly digital
measurements, their capabilities
are best employed for looking at
problems that are both functional
and parametric in nature – for
example, triggering on a digital bus
and having this trigger condition
arm the scope measurement.
At Agilent, one of our design
teams experienced an infrequent
software glitch on an embedded
product under development. This
anomaly manifested itself very infrequently
– about once a week. The software
team developed diagnostics that
caused the problem to happen on a more
frequent basis. With this diagnostic software,
they found that the problem
occurred during read cycles on a PCI bus
embedded in an FPGA.
The team routed PCI status signal out
to pins and connected the MSO’s digital
channels to these signals. Engineers quickly
set up the MSO digital trigger on a PCI
read cycle and then set the MSO scope
channels to acquire when the MSO digital
channels recorded a PCI bus read cycle.
With the ability to trigger on a specific
bus cycle, the team was quickly able to
resolve the problem. They found a clock
with a too-slow rise time that impacted primarily
read cycles. The team modified the
design and downloaded a new configuration
file into the FPGA. The combination of
reprogrammable FPGAs and MSO measurements
allowed the design team to fix the
problem and ship the product on schedule.
Extensive Internal Visibility
To access internal signals, you might typically
use the route-out approach to bring signals
to pins that can be probed using an
oscilloscope. Using traditional oscilloscopes,
you would have access to either two or four
Figure 1 – In addition to scope channels, mixed-signal oscilloscopes
provide 16 digital channels. This gives you the ability to trigger
and display as many as 20 signals simultaneously. The width of
the digital channels is particularly well suited for measuring
signals internal to Xilinx FPGAs.
signals at a time. This narrow signal visibility
can complicate debug, as a number of problems
require simultaneous visibility across a
higher number of signals. To access new signals,
you must change the design, re-synthesize,
and run a new place and route to make
your signals accessible to the oscilloscope.
This process can take hours.
With the digital channels of an MSO,
you have visibility of as many as 16 internal
FPGA signals at a time. The power of the
MSO’s digital channels can be further
extended when combined with on-chip
technologies such as the Xilinx
ChipScope Pro tool and Agilent FPGA
Dynamic Probe.
The ChipScope Pro analyzer allows
design teams to incorporate an Agilent
DEBUGGING
debug core in their FPGA designs. The
debug core, known as ATC2, provides an
easy way to route signals to pins, enables a
faster setup of the MSO, and allows you to
quickly measure new groups of internal signals.
This capability extends the reach of the
16 digital channels into the FPGA design.
Let’s look at a simple communication
system to illustrate the value of an MSO’s
digital channels for FPGA debug. A state
machine drives the process of sending out
packets of 16-bit data along with a transaction
ID. Parallel data is serialized, sent on a
serial channel, de-serialized, and brought
into a monitor. A second state
machine at the monitor drives the
process of receiving the packets
and strips off the data and transaction
IDs so that the packets can be
pulled off to external memory.
This state machine also generates
acknowledge IDs that are fed back
to the transmit side to communicate
that data was received. The
design originally dedicated 16 pins
for a debug port.
Using the ChipScope Pro core
inserter, you can parameterize an
ATC2 core. A benefit of the core
inserter is that you need not modify
the original HDL design, as
core insertion occurs post-synthesis
and before place and route.
You would simply specify, using
the core inserter, which internal
signals to group together as an active signal
bank. Place and route uses the original
user constraint file, so no additional work
is required.
The core inserter also produces a small
file that contains the specified signal names
and groups. This file, known as a .cdc, is
read by the FPGA Dynamic Probe application
running on the MSO. When changing
which signal group is presented to the
MSO, the instrument automatically uses
this signal naming file to correctly update
signal names on the display. As opposed to
the route-out approach, which can take
hours to bring new signals to pins, the
FPGA Dynamic Probe allows you to access
a new group of internal signals in about
one second.
Third Quarter 2005 Xcell Journal 99