Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

SYSTEM PERFORMANCE
A(47:0)
CLK
Mapping Beyond Multipliers
Precision Synthesis automatically infers
and maps all multiplier and arithmetic
operators into DSP48 where possible. In
DSP designs, however, critical data paths
are not necessarily always lying on multipliers.
Adders, subtractors, counters, and
other operators could also be the source of
the critical timing path. To help deal with
these situations, Precision Synthesis lets
you control each arithmetic operator by
D
Q
+ D Q
Figure 6 – RTL schematic for a simple INCDEC design
individually manipulating the mapping.
These features deliver two main advantages:
• An extra boost in solving timing problems
when necessary.
• DSP mapping controllability when
desired because of resource availability
and timing requirements.
Precision Synthesis gives you the
option to map the following operators
into a DSP48 slice. Figure 6 shows the
Figure 7 – Setting the use_resource attribute in Precision Synthesis
PREG(47:0)
RTL schematic of a DEC operator:
• Adder/subtractor/addsub – default to
CARRY CHAIN and/or LOGIC
• INC/DEC/INCDEC – default to
CARRY CHAIN and/or LOGIC
• EQ/NEQ/LT/LTE/GT/GTE – default
to CARRY CHAIN and/or LOGIC
• Counter – default to CARRY CHAIN
and/or LOGIC
• Mult/mult-add/mult-acc – default to
DSP48
You can map the DEC operator into a
DSP48 slice by using the Precision Synthesis
GUI (Figure 7) or interactive command line
as follows:
• From the RTL hierarchical browser,
right-click on the DEC operator. Select
Set Attributes > New.
• Enter attribute name and value.
• You can use the command line to accomplish
the same task: set_attribute -design
rtl -name use_resource -value DSP48 -
instance rtlc_1_dec_0.
Conclusion
For MULT-ACC with adder/subtractor and
multiple stages of internal input pipeline
registers, the Xilinx Virtex-4 architecture
has specific advantages over other vendors.
For wide multipliers without accumulators,
you may find that DSP48 in Virtex-4
devices and other DSP vendors compete
more closely in terms of performance. But
regardless of your design application, it
would be beneficial to test-drive the DSP48
functions in tandem with the Mentor
Graphics Precision Synthesis tool for your
next design project.
By supporting advanced DSP48 inferencing
capabilities, Precision Synthesis makes it
possible to easily model DSP RTL behavior
at a very high level. It also provides added
flexibility with RTL coding styles. The
DSP48 inference capability in Precision
Synthesis, combined with the advanced
DSP48 slice in Virtex-4 FPGAs, provides a
powerful system solution if you are considering
designing in DSP with today’s advanced
FPGA architectures.
28 Xcell Journal Third Quarter 2005