Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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CONNECTIVITY Connecting Intel StrataFlash Memory to Spartan-3E FPGAs You can gluelessly connect the Spartan-3E FPGA to the low-cost and high-density Intel StrataFlash Memory. by Ying Sue Senior Technical Marketing Engineer, Flash Products Group Intel ying.sue@intel.com The Xilinx ® Spartan-3E family of FPGAs targets high-volume, cost-sensitive consumer electronic applications with a density range from 100,000 to 1.6 million system gates. It offers performance and cost enhancements over the previous generation of Spartan devices, as well as a new configuration mode allowing a glueless interface to standard parallel NOR flash memories. Nearly all of the configuration pins can be used as user I/Os after configuration. This configuration mode, known as the byte-wide peripheral interface (BPI) parallel flash mode, lets you take advantage of low-cost and high-density Intel StrataFlash 3V Memory (J3), or J3 Memory. J3 Memory uses Intel ETOX process technology with multi-level cell capability, which provides 2X the bits in 1X the space. J3 Memory is available in a variety of pack- 72 Xcell Journal Third Quarter 2005
ages and densities for increased flexibility and can be gluelessly connected to the Spartan-3E FPGA to store any of the following: • Bitstreams for one or more FPGAs • Boot code, parameters, and data for soft CPU cores in the FPGA • Multiple bitstreams for the same FPGA utilizing the MultiBoot feature of the Spartan-3E device Figure 1 shows how dual bitstreams (for MultiBoot) and code/data storage can coexist in a J3 Memory device. Design Notes Figure 2 illustrates the connection between two Spartan-3E FPGAs and a J3 Memory flash device in a 3.3V environment. In this section, we’ll examine key design considerations, such as power sequence, reset, hot-swap, flash content protection, and x8/x16 mode toggling. Power-Up Sequence Three supply voltages are required to support the Spartan-3E device and J3 Memory in a 3.3V application: • 3.3V: connected to the VCC and VCCQ supplies of J3 Memory, as well as to the VCCO_1 and VCCO_2 supplies of the FPGA • 2.5V: connected to the VCCAUX supply of the FPGA • 1.2V: connected to the VCCINT supply of the FPGA VCCO_0 and VCCO_3 supplies of the FPGA can be 3.3V, 2.5V, 1.8V, 1.5V, or 1.2V, as required by the application. The Spartan-3E FPGA datasheet describes the power-on precaution in the serial flash mode (SPI mode), where the FPGA might be reading from the flash device before the flash memory is ready. The same consideration applies to parallel flash devices, because typical flash devices require some time (60 µs for J3 Memory) to complete internal initialization after the voltage reaches a nominal level (2.7V for J3 Memory). If the 2.5V and 1.2V are valid and the 3.3V reaches 0.4V to 1.0V (a voltage level below the minimum operating voltage of a flash device such as J3 Memory), the FPGA starts its programming sequence before the flash device is ready. Either of two scenarios might occur: • 3.3V is valid (reaching 2.7V) before 2.5V and 1.2V reach their minimum Intel StrataFlash Memory (J3) TDO TMS TCK FPGA Application Bitstream Soft CPU Core Boot & Application Code + Data 0x1FFFFF STARTUP_SPARTAN3E required voltage. This scenario typically does not cause issues because the flash device (such as J3 Memory) is ready for reading when the FPGA starts its programming sequence. • 3.3V is valid after 2.5V and 1.2V. To work around this scenario, you can typically use a 3.3V voltage monitor to hold the PROG_B or INIT_B pin FPGA Application Bitstream Soft CPU Core Boot & Application Code + Data FPGA Diagnostics FPGA Diagnostics Bitstream Bitstream First Configuration 0x00000 0 Second Configuration 0x1FFFFF 0x000000 Third Quarter 2005 Xcell Journal 73 >300 ns GSR GTS MBT CLK Intel StrataFlash Memo ry (J3) For more information on using the Xilinx Spartan-3E FPGA in this setup, see Xilinx datasheet DS312-2 JTAG Header Optional 3.3V Monitor Open Drain POR (>1ms Delay) 3.3V 330 BPI Mode 4.7K 0 1 0/1 0 0 TDI 0 CCLK CSI_B 1 1 0 CSI_B 0 TDI TMS TCK TDO 0 CCLK Xilinx Spartan-3E M2 M1 M0 CSI_B RDWR_B TDI TMS TCK TDO HSWAP CCLK CSO_B PROG_B DONE Slave Parallel Mode M2 M1 M0 CSI_B RDWR_B TDI TMS TCK TDO HSWAP CCLK CSO_B PROG_B DONE GND VCCO_1 VCCO_2 LDC0 LDC1 HDC LDC2 A[23:0] D[7:0] INIT_B VCCAUX USER I/Os VCCINT VCCO_1 VCCO_2 D[7:0] INIT_B VCCAUX USER I/Os VCCINT Xilinx Spartan-3E 2.5V 1.2V 3.3V 2.5V 1.2V 4.7K Intel StrataFlash Memory (J3) 340 Optional 3.3V CONNECTIVITY Figure 1 – Multiple bitstream and code/data storage in flash devices (B4980) CE0 OE# WE# BYTE# A[23:0] D[7:0] D[15:8] VCC VCCQ RP# VPEN STS CE1 CE2 GND 3.3V 4.7K 4.7K Figure 2 – A 2x Xilinx Spartan-3E FPGA to Intel StrataFlash memory (J3) connection (B4981)
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Xcell Issue 54 Third Quarter 2005 j
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EDITOR IN CHIEF Carlis Collins edit
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THIRD QUARTER 2005, ISSUE 54 Xcell
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Hardware Said ... The design flow s
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The second idea is to have the hard
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and automatic module generation wil
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Designing Control Circuits for High
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Figure 2 - Implementing an FSM in S
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Let’s consider these challenges i
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demonstrated by Dr. Howard Johnson,
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