Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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$ The design fits nicely (~75% utilization) in a CoolRunner-II 32-macrocell device, leaving ~25% headroom for other possible functions. Plus, there are additional design ideas that can reduce power and make use of CoolRunner-II powersaving features. Clk Processor GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 Encoded Input to Processor TOTAL COST en0 en1 en2 en3 en4 en5 CLK CPLD 8 8 Row Encoder Column Encoder CPLD Design Details To scan the keypad rows, a barrel shift register is initialized with all ones, except for a single bit preset to zero. Each bit of the shift register drives an output pin of the CPLD that is connected to a row of the keypad. As the shift register is 8 x 8 Keypad Figure 3 – GPIO expansion with a CoolRunner-II CPLD Shift Register en clk 1 1 1 1 1 0 1 1 Figure 4 – Block diagram Row Outputs to Keypad (8x8) Column Inputs from Keypad (8x8) clocked, the zero bit shifts through the barrel shifter and scans the rows by driving them low one at a time. The keypad columns are inputs to the CPLD and each input is pulled up through an internal pull-up resistor. When no keys are being pushed, all column inputs to the CPLD are passively pulled up to logic high. All the column inputs are AND’d together and a logic one at the output indicates that no keys are being pressed. The output of the AND is used as an enable to the shift register. When a key is pressed, the connection between the row and column is made and the column with the key being pressed is driven low by the row associated with that key. The output of the AND will go low and disable the shift register when the key is pressed. At this point the shift register is driving the row of the key being pressed to a low, and the column of that key is also at a low. To correlate this information, two encoders are used: one for the row bits (outputs of the shift register) and another for the column inputs. The outputs of the two encoders are grouped together to form the encoded word that is sent to the processor. Figure 4 shows a block diagram of the operation. Conclusion By using Xilinx CoolRunner-II CPLDs, you get design flexibility and low power. Besides I/O expansion, other “glue” functions can be absorbed into the CPLD, such as voltage translation, I/O standards translation, and input hysteresis. Because CPLDs are programmable, you can use the same device with different keypads and in different products, leading to higher volume quantities and lower cost. The ability to reprogram them (along with simple-to-use design tools) allows for late design changes and lower risk. To learn more about this application, see the Xilinx application note, “Implementing Keypad Scanners with CoolRunner-II,” at www.xilinx.com/ bvdocs/appnotes/xapp512.pdf. For more information about Xilinx CPLDs, visit www.xilinx.com/cpld/. 34 Xcell Journal Third Quarter 2005
FPGA-Based Video Games Implementing video games in FPGAs is fun and educational. by Eric Crabill Staff Design Engineer Xilinx, Inc. eric.crabill@xilinx.com In an attempt to help me maintain a better work/life balance, my wife suggested that I pick up a hobby. The first thing that came to mind was developing FPGA-based video games. I have never been a good game player, but I am fascinated by game hardware. The reason I studied electrical engineering in the first place was to get a job at Atari Games, but they closed their doors before I earned my degree. Silicon, software, and solutions from Xilinx ® are all you need to develop game platforms and write games. You can get started for less than $100 with the Xilinx Spartan-3 Starter Kit and ISE WebPACK software. Implementing video games in FPGAs is not only fun, it creates an opportunity to learn more about FPGA devices and development tools through experimentation – without the stress of deadlines. Third Quarter 2005 Xcell Journal 35 $ TOTAL COST
Page 1 and 2: Xcell Issue 54 Third Quarter 2005 j
Page 3 and 4: EDITOR IN CHIEF Carlis Collins edit
Page 5 and 6: THIRD QUARTER 2005, ISSUE 54 Xcell
Page 7 and 8: Hardware Said ... The design flow s
Page 9 and 10: The second idea is to have the hard
Page 11 and 12: and automatic module generation wil
Page 13 and 14: Designing Control Circuits for High
Page 15 and 16: Figure 2 - Implementing an FSM in S
Page 17 and 18: Let’s consider these challenges i
Page 19 and 20: demonstrated by Dr. Howard Johnson,
Page 21 and 22: Pblocks can direct the flow of the
Page 23 and 24: Virtex-4 beats competing FPGAs in e
Page 25 and 26: In addition, you may also use techn
Page 27 and 28: Using Precision Sythesis, Block Mul
Page 29 and 30: 14-Bit, 125Msps ADC Only 395mW Lowe
Page 31 and 32: Non-Symmetric Aspect Ratios/FWFT Ap
Page 33: QWERTY Building Blocks Our solution
Page 37 and 38: The Atari 2600 Video Computer Syste
Page 39 and 40: The architecture wizards inside ISE
Page 41 and 42: Smart Telematics Systems from Xilin
Page 43 and 44: interfaces available, Microsoft int
Page 45 and 46: TXPLL TxData[7:0] FIFO an x4 link c
Page 48 and 49: POWER MANAGEMENT Design Techniques
Page 50 and 51: Power Estimation Tools Xilinx provi
Page 52 and 53: POWER MANAGEMENT Performance vs. Po
Page 54 and 55: POWER MANAGEMENT is the first time
Page 56 and 57: POWER MANAGEMENT Merging CPLD Featu
Page 58: POWER MANAGEMENT A Clear Choice Wit
Page 62 and 63: POWER MANAGEMENT Spartan-3 FPGA Pow
Page 64: POWER MANAGEMENT 5 V_INPUT Highly i
Page 67 and 68: Tool Example Electrical Simulations
Page 69 and 70: y Bill Hargin Product Manager, Hype
Page 71 and 72: Typically used bit patterns, or “
Page 73 and 74: ages and densities for increased fl
Page 75 and 76: see the start sequence, it continue
Page 77 and 78: The Virtex-4 ML450 Development Boar
Page 79 and 80: CONNECTIVITY Bridging System Packet
Page 81 and 82: put stream of SPI-4.2 data. A progr
Page 83 and 84: Controlling Noise A well-designed p
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Prototype Your PCIe ASIC HERE See u
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knowing what is in R3 of the proces
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X-ray X-ray vision vision for for y
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The program size is smaller because
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Communications) and Verilog PLI, so
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Figure 1 - Period constraint in Syn
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DEBUGGING Using the actual constrai
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Bus Triggering and Display Traditio
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Designer Challenges for Pb-Free and
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A Shortcut to Effective Hierarchica
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Xilinx Education Services: Knowledg
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BIDIR_PAD(7.0) BIDIR this course, w
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Xesium Global Clocking • 500MHz D
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Xilinx Virtex-4 FPGAs www.xilinx.co
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Xilinx CPLD www.xilinx.com/devices/
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Design Example: 1.5 volt LVCMOS 4mA
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Design Challenges: Avoiding the Pitfalls, winning the game - Xilinx

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